Maksim Kiselev [Wed, 11 Dec 2024 20:11:00 +0000 (23:11 +0300)]
riscv: dts: t-head: Add sdhci and emmc nodes
Add SDHCI and EMMC controlles nodes on TH-1520 SoC. And enable them for
Lichee module 4A.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Maksim Kiselev [Wed, 11 Dec 2024 20:10:59 +0000 (23:10 +0300)]
mmc: snps_sdhci: Add sdhci driver support for TH1520 SoC
Add support for DesignWare SDHCI host controller on Alibaba TH1520 SoC
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Hal Feng [Sun, 8 Dec 2024 09:19:42 +0000 (17:19 +0800)]
riscv: cpu: jh7110: Sort the list of imply statements
The imply statements should be sorted in the sequence
of appearance in .config.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:41 +0000 (17:19 +0800)]
board: starfive: spl: Support multiple DTBs for JH7110 based boards
Get product ID and the other information from EEPROM, use them to select
the correct DTB.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:40 +0000 (17:19 +0800)]
board: starfive: spl: Fix the wrong use of CONFIG_IS_ENABLED()
The prefix "SPL_" is not needed when using CONFIG_IS_ENABLED().
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Fixes:
5ecf9b0b8a75 ("board: starfive: add StarFive VisionFive v2 board support")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:39 +0000 (17:19 +0800)]
riscv: dts: jh7110: Support multiple DTBs in a Fit image
Support multiple DTBs for JH7110 based boards, so they can
select the correct DT at runtime.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:38 +0000 (17:19 +0800)]
configs: visionfive2: Enable MULTI_DTB_FIT for JH7110 based board DT
So JH7110 based boards can select their own DT at runtime.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:37 +0000 (17:19 +0800)]
board: starfive: spl: Drop the unneeded DT modification code
As OF_UPSTREAM is implemented, these code are redundant.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:36 +0000 (17:19 +0800)]
riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards
To support the other JH7110 based boards, add u-boot
device tree for them.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: H Bell <dmoo_dv@protonmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:35 +0000 (17:19 +0800)]
riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsi
To support JH7110 based boards besides v1.3B,
add a common dtsi and add common code to it.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:34 +0000 (17:19 +0800)]
pcie: starfive: Make the driver compatible with upstream DT
There are difference between upstream DT and the old DT
in terms of reg base, reset gpio and syscon. Make the driver
compatible with upstream DT.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:33 +0000 (17:19 +0800)]
mmc: dw_mmc: Add "starfive, jh7110-mmc" compatible to match upstream DT
Make the U-Boot JH7110 MMC driver compatible with upstream DT.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:32 +0000 (17:19 +0800)]
riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT
Add u-boot features to the U-Boot device tree.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:31 +0000 (17:19 +0800)]
dts: starfive: Switch to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.
Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.
Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Thomas Bonnefille [Tue, 12 Nov 2024 14:57:38 +0000 (15:57 +0100)]
board: add support for LicheeRV Nano
The LicheeRV Nano is a small SBC using the Sophgo SG2002 RISCV SoC.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Thomas Bonnefille [Tue, 12 Nov 2024 14:57:37 +0000 (15:57 +0100)]
riscv: dts: sophgo: add device tree for LicheeRV Nano
Import a slightly modified version of the LicheeRV Nano and SG2002
device trees from the Linux Kernel. The current supported IPs are UART,
MMC, Timer, PLIC and CLINT.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Thomas Bonnefille [Tue, 12 Nov 2024 14:57:36 +0000 (15:57 +0100)]
doc: add LicheeRV Nano and SG2002 SoC
Provide a page describing the usage of U-Boot on the LicheeRV Nano and a
description of the board.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Peng Fan [Tue, 3 Dec 2024 13:42:57 +0000 (21:42 +0800)]
smbios: address build warning
include display_options.h to address build warning:
lib/smbios.c: In function ‘smbios_update_version’:
lib/smbios.c:305:9: warning: implicit declaration of function ‘print_buffer’
[-Wimplicit-function-declaration]
print_buffer((ulong)ptr, ptr, 1, old_len + 1, 0);
^~~~~~~~~~~~
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Prasanth Babu Mantena [Wed, 27 Nov 2024 06:13:34 +0000 (11:43 +0530)]
arm: mach-k3: fix typo in devstat macro name
Fix spelling mistake in the board init files of j721e and j721s2.
s/WKUP_DEVSTAT_MCU_OMLY_MASK/WKUP_DEVSTAT_MCU_ONLY_MASK
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Yuri Zaporozhets [Sun, 1 Dec 2024 22:28:49 +0000 (23:28 +0100)]
bios_emulator: fix incorrect printing of address in "jump near immediate"
In the x86emuOp_jump_call_near_IMM() function the target address is
printed incorrectly when jumping backwards. For example instead of
"jmp 0xe8bc" the string "jmp
ffffe8bc" is printed. That's because
of the following macro:
DECODE_PRINTF2("%04x\n", ip);
while it should be
DECODE_PRINTF2("%04x\n", (u16)ip);
Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
Yuri Zaporozhets [Sat, 30 Nov 2024 20:56:25 +0000 (21:56 +0100)]
bios_emulator: fix incorrect printing of address in "call near immediate"
In the x86emuOp_call_near_IMM() function the address of CALL is
printed incorrectly when jumping backwards. For example, the correct
disassemble of the bytes below would be:
0000E8DE E8DBFF call 0xe8bc
(verified by ndisasm). But instead the address is printed as "
ffffe8bc".
That's because of the following macro:
DECODE_PRINTF2("%04x\n", ip);
while it should be
DECODE_PRINTF2("%04x\n", (u16)ip);
Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
Yuri Zaporozhets [Tue, 26 Nov 2024 23:29:53 +0000 (00:29 +0100)]
bios_emulator: fix garbled printing of disassembled SET* instructions
When DEBUG_DECODE_F is enabled in bios_emulator, the printing of
SET{O,NO,B,NB,Z,NZ,BE,NBE,S,NS,P,TP,L,NL,LE,NLE} instructions
is not followed by newline and is, therefore, immediately followed
by the printed address of a new instruction. This garbles the output
and makes it very difficult to read.
This patch adds missing DECODE_PRINTF("\n") calls to print newlines.
Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
Yuri Zaporozhets [Tue, 26 Nov 2024 21:59:37 +0000 (22:59 +0100)]
bios_emulator: fix garbled printing of disassembled BSF instruction
When DEBUG_DECODE_F is enabled in bios_emulator, the printing of BSF
instructions is garbled because the '\n' symbol is used instead of
the correct '\t'. Fix that.
Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
Tom Rini [Sat, 14 Dec 2024 15:34:27 +0000 (09:34 -0600)]
Merge patch series "Hyperflash Boot fixes for J7200/J721E"
Anurag Dutta <a-dutta@ti.com> says:
Hi All,
In u-boot, hbmc is broken and has been removed from j7200
configs. This series re-enables the hbmc driver and introduces a series
of hyperflash boot fixes. At present, in u-boot, the parent device (fss)
gets registered as a syscon device. This is done because the MMIO
mux driver in u-boot did not support the mux functionality when the
parent device is not a syscon. In this series, we make relevant changes
in the hbmc driver as well as dts' so that we can use the reg-mux driver for
selecting the appropriate state of the mux.
Test logs:
1) j721e-idk-gw hyperflash boot test: https://gist.github.com/anuragdutta731/
50aae6fec707a3ffad6d985de6757fe4
2) j7200-evm hyperflash boot test: https://gist.github.com/anuragdutta731/
c3a4d60f8bfd9c425d6c44b36eb7322b
Link: https://lore.kernel.org/r/20241129113136.383277-1-a-dutta@ti.com
Anurag Dutta [Fri, 29 Nov 2024 11:31:36 +0000 (17:01 +0530)]
mtd: Kconfig: Change HBMC driver's dependency to MULTIPLEXER and MUX_MMIO
The HBMC_AM654 driver was dependent on SYSCON because syscon APIs were
being used to select the multiplexer state. Change the dependency to
MULTIPLEXER and MUX_MMIO because mux APIs are now being used to
select mux state.
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Vaishnav Achath [Fri, 29 Nov 2024 11:31:35 +0000 (17:01 +0530)]
configs: j7200_evm_*_defconfig: Add configs for Hyperflash boot
Kernel commit
dbb124cf6888 ("configs: j7200: Remove HBMC_AM654
config") removed the HBMC_AM654 config because hbmc was broken
in u-boot. Hence, add the missing configs necessary to re-enable
Hyperflash boot.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Aswath Govindraju [Fri, 29 Nov 2024 11:31:34 +0000 (17:01 +0530)]
include: configs: j721e_evm: Increase memory offset for tiboot3.bin in HyperFlash
The size of J7200 tiboot3.bin is 516KB but the memory reserved for it in
HyperFlash was 512KB. This led to overlap of tiboot3.bin over tispl.bin
region and break in HyperFlash boot mode.
Therefore, fix this by increasing the memory allocated for tiboot3.bin
to 1MB for J7200.
Fixes:
cf1d6867f774 ("board: ti: j7200: Introduce support for j7200 build targets")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Vaishnav Achath [Fri, 29 Nov 2024 11:31:33 +0000 (17:01 +0530)]
configs: j721e_evm_*_defconfig: Add configs for Hyperflash boot
Kernel commit
5b2671594b80 ("configs: j721e: Remove HBMC_AM654
config") removed the HBMC_AM654 config because hbmc was broken
in u-boot. Hence, add the missing configs necessary to re-enable
Hyperflash boot.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Vaishnav Achath [Fri, 29 Nov 2024 11:31:32 +0000 (17:01 +0530)]
arm: dts: k3-j721e-r5-common: Add HBMC overrides for R5 SPL
Add 32-bit address overrides for Hyper Bus Memory Controller
for Hyperflash to be functional in R5 SPL.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Vaishnav Achath [Fri, 29 Nov 2024 11:31:31 +0000 (17:01 +0530)]
arm: dts: k3-j7200-r5-common: Add HBMC overrides for R5 SPL
Add 32-bit address overrides for Hyper Bus Memory Controller
for Hyperflash to be functional in R5 SPL.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Anurag Dutta [Fri, 29 Nov 2024 11:31:30 +0000 (17:01 +0530)]
mtd: HBMC-AM654: Changed syscon API to mux APIs
The syscon APIs were used for selecting the state of the mux
device because the mmio-mux driver in u-boot did not support
the mux functionality when the parent device is not a syscon.
Change to mux APIs which utilizes the reg-mux driver to select the
state of the multiplexer.
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Anurag Dutta [Fri, 29 Nov 2024 11:31:29 +0000 (17:01 +0530)]
mux: Makefile: Add config for mux drivers
Add config required to build mmio-mux driver and dependencies.
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Tom Rini [Sat, 14 Dec 2024 15:33:18 +0000 (09:33 -0600)]
Merge patch series "configs: Enable CMD_NFS by default"
Neha Malcom Francis <n-francis@ti.com> says:
Enable the NFS command across all platforms to allow network booting via
the NFS. Clean up the J7 configs to use TI_COMMON_CMD_OPTIONS.
Link: https://lore.kernel.org/r/20241129110333.444270-1-n-francis@ti.com
Neha Malcom Francis [Fri, 29 Nov 2024 11:03:33 +0000 (16:33 +0530)]
configs: j7*: Enable TI_COMMON_CMD_OPTIONS
Instead of bloating the defconfig with CONFIG_CMD_*, move J7 devices to
start using TI_COMMON_CMD_OPTIONS.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Neha Malcom Francis [Fri, 29 Nov 2024 11:03:32 +0000 (16:33 +0530)]
board: ti: common: Kconfig: Add CMD_NFS
Add CMD_NFS to list of configs implied by CONFIG_TI_COMMON_CMD_OPTIONS.
This allows network booting via the NFS protocol from the U-Boot prompt.
Fixes:
10de12570799 ("disable NFS support by default")
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Tom Rini [Sat, 14 Dec 2024 15:33:03 +0000 (09:33 -0600)]
Merge patch series "UART support for higher baudrate"
Gokul Praveen <g-praveen@ti.com> says:
The OMAP specific UART driver is changed from a generic implementation of
certain ops functions to an OMAP specific implementation of it to add
support for higher baudrates for OMAP devices.
Hence to support the above change, static functionality of ops functions
in generic ns16550 UART U-Boot driver is removed and also migrated certain
macros to its header file for usage in device-specific drivers.
Boot logs link :
https://gist.github.com/GOKU-THUG/
8b90117c963e5da5c1b6caeee427c82c
Link: https://lore.kernel.org/r/20241126105131.43359-1-g-praveen@ti.com
Gokul Praveen [Tue, 26 Nov 2024 10:51:31 +0000 (16:21 +0530)]
drivers: serial: serial_omap: Fix TI OMAP UART U-Boot driver to support higher baudrates
Move to OMAP specific implementation of certain ops functions as the UART
prints on the serial console fail for baudrates greater than 460800.
The MDR1 register is responsible for determining the speed mode at which
the UART should operate for OMAP specific devices. The baud divisor is used
to set the UART_DLL register which is used for generation of the baud
clock in the baud rate generator. The implementation logic is similar to
how it is implemented in omap_8250_get_divisor function of 8250_omap UART
linux driver.
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Gokul Praveen [Tue, 26 Nov 2024 10:51:30 +0000 (16:21 +0530)]
serial: ns16550: Increase scope of ops functions
Increase scope of ops functions and do some clean up for usage in device
-specific UART drivers.
Remove the static functionality of ops functions and migrate certain macros
to header file for usage in device-specific drivers.
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 13 Dec 2024 23:30:27 +0000 (17:30 -0600)]
Merge patch series "Add phyCORE AM62Ax"
Garrett Giordano <ggiordano@phytec.com> says:
This patch set adds the phyCORE AM62Ax board support and documenation to
u-boot.
The phyCORE-AM62Ax is a SoM (System on Module) featuring TI's AM62Ax SoC. It can
be used in combination with different carrier boards. This module can come
with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs
from the AM62x family.
A development Kit, called phyBOARD-Lyra is used as a carrier board reference
design around the AM62x SoM.
This series depends on the following two patches:
- [PATCH v2] arm: mach-k3: am62a7: Provide a way to obtain boot device for non SPL
https://lists.denx.de/pipermail/u-boot/2024-October/570156.html
- [PATCH] board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCH
https://lists.denx.de/pipermail/u-boot/2024-November/571543.html
Link: https://lore.kernel.org/r/20241118231606.3161665-1-ggiordano@phytec.com
[trini: Fix warning in board/phytec/common/k3/board.c when
CONFIG_EFI_HAVE_CAPSULE_SUPPORT is not enabled]
Signed-off-by: Tom Rini <trini@konsulko.com>
Garrett Giordano [Thu, 31 Oct 2024 16:21:03 +0000 (09:21 -0700)]
arm: mach-k3: am62a7: Provide a way to obtain boot device for non SPLs
Introduce get_boot_device() to obtain the booting device. Make it also
available for non SPL builds so u-boot can also know the device it
is booting from.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Vitor Soares [Mon, 25 Nov 2024 17:49:10 +0000 (17:49 +0000)]
toradex: tdx-cfg-block: rework modules pid4 handling
The module pid4 currently corresponds to the index of the toradex_module
array. If a new pid4 is introduced that does not follow the sequence of
the previous entries, it will create a gap in the array.
To address this, embed pid4 within the toradex_som structure and
implement a function to retrieve the index corresponding to pid4.
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Garrett Giordano [Mon, 18 Nov 2024 23:16:06 +0000 (15:16 -0800)]
doc: board: phytec: Add phyCORE-AM62ax
Add documentation for PHYTEC phyCORE-AM62ax SoM.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Garrett Giordano [Mon, 18 Nov 2024 23:16:05 +0000 (15:16 -0800)]
board: phytec: am62a7: Add PHYTEC phyCORE-AM62A7 SoM
Add support for PHYTEC phyCORE-AM62A7 SoM.
Supported features:
- 2GB LPDDR4 RAM
- eMMC
- External SD
- Ethernet
- debug UART
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Tom Rini [Fri, 13 Dec 2024 20:15:43 +0000 (14:15 -0600)]
Merge patch series "Enable EFI capsule updates for PHYTEC K3 SoMs"
Wadim Egorov <w.egorov@phytec.de> says:
This implements capsule updates for all our K3 SoMs for
eMMC, OSPI NOR and uSD cards.
We can use capsule updates to update the bootloader on all our
supported flash devices.
Link: https://lore.kernel.org/r/20241127121736.1525948-1-w.egorov@phytec.de
Wadim Egorov [Wed, 27 Nov 2024 12:17:36 +0000 (13:17 +0100)]
configs: phycore_am6*_a53_defconfig: Enable capsule update
Enable raw & on disk capsule updates and provide configs required
for updating MTD devices. Also resync after savedefconfig.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Wadim Egorov [Wed, 27 Nov 2024 12:17:35 +0000 (13:17 +0100)]
board: phytec: k3: Add EFI capsule update support
Implement EFI capsule update functionality for PHYTEC K3-based SoMs.
These SoMs feature various flash device options, including eMMC,
OSPI NOR, and uSD card at the board level.
This update provides the necessary logic to enable EFI capsule updates
across all three flash devices, ensuring flexible and robust firmware
upgrade capabilities.
The GUID is dynamically generated for the board, to get it:
efidebug capsule esrt
========================================
ESRT: fw_resource_count=3
ESRT: fw_resource_count_max=3
ESRT: fw_resource_version=1
[entry 0]==============================
ESRT: fw_class=
C7D64D6D-10B2-54BC-A3BF-
06A9DC3653D9
ESRT: fw_type=unknown
ESRT: fw_version=0
ESRT: lowest_supported_fw_version=0
ESRT: capsule_flags=0
ESRT: last_attempt_version=0
ESRT: last_attempt_status=success
[entry 1]==============================
ESRT: fw_class=
09841C3F-F177-5D57-B1F6-
754D92879205
ESRT: fw_type=unknown
ESRT: fw_version=0
ESRT: lowest_supported_fw_version=0
ESRT: capsule_flags=0
ESRT: last_attempt_version=0
ESRT: last_attempt_status=success
[entry 2]==============================
ESRT: fw_class=
D11A9016-515E-503A-8872-
3FF65384D0C4
ESRT: fw_type=unknown
ESRT: fw_version=0
ESRT: lowest_supported_fw_version=0
ESRT: capsule_flags=0
ESRT: last_attempt_version=0
ESRT: last_attempt_status=success
========================================
On the board (from uSD card containing capsule binaries at boot):
load mmc 1:1 $loadaddr tiboot3-capsule.bin
efidebug capsule update $loadaddr
load mmc 1:1 $loadaddr tispl-capsule.bin
efidebug capsule update $loadaddr
load mmc 1:1 $loadaddr uboot-capsule.bin
efidebug capsule update $loadaddr
The binaries will be flashed to the flash device you are booted from.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Wadim Egorov [Wed, 27 Nov 2024 12:17:34 +0000 (13:17 +0100)]
arm: dts: k3-am642-phycore-som-binman: Provide capsule nodes
Fill in phycore-am64x capsule GUID properties of the base
binman capsule nodes.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Wadim Egorov [Wed, 27 Nov 2024 12:17:33 +0000 (13:17 +0100)]
arm: dts: k3-am625-phycore-som-binman: Provide capsule nodes
Fill in phycore-am62x capsule GUID properties of the base
binman capsule nodes.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tom Rini [Fri, 13 Dec 2024 20:14:50 +0000 (14:14 -0600)]
Merge patch series "AM62A DWC3: Add support for USB DFU boot in OTG mode"
Siddharth Vadapalli <s-vadapalli@ti.com> says:
Hello,
This series adds support for USB DFU boot on TI's AM62A SoC which has
two instances of DWC3 USB Controllers namely USB0 and USB1. The USB0
instance of the USB Controller supports USB DFU boot:
ROM => tiboot3.bin => tispl.bin => u-boot.img
USB DFU Boot requires the USB Controller to be configured for Gadget
mode of operation. Since the USB0 instance of the DWC3 USB Controller
supports both Host and Gadget modes of operation via the Type-C interface
on the AM62A7-SK board, the device-tree specifies the "dr_mode" as "OTG".
However, there is currently no support for dynamically switching the "mode"
from Host to Gadget and vice-versa with the help of a state-machine.
The OTG mode is treated as a separate mode in itself rather than being
treated as an intermediate stage before assuming the Host/Gadget mode.
Due to this, USB DFU boot via the Type-C interface doesn't work as the
USB Controller hasn't been appropriately configured for Device/Gadget
mode of operation. One option is to change the device-tree to specify
"dr_mode" as "peripheral" and force the controller to assume the Device
role. This will imply that the U-Boot device-tree for AM62A diverges
from its Linux counterpart. Therefore, with the intent of keeping the
device-tree uniform across Linux and U-Boot, and at the same time, in
order to enable USB DFU boot in "OTG" mode with the DWC3 Controller,
the first patch in this series sets the "mode" on the basis of the
caller function, rather than using the "dr_mode" property in the
device-tree. There are only two callers of "dwc3_generic_probe()",
each of which clearly specify the expected mode of configuration.
This will enable both Host and Device mode of operation based on the
command executed by the user, thereby truly supporting "OTG"
functionality when the USB Controller supports it.
The second patch in this series adds USB DFU environment for AM62A,
enabling USB DFU Boot and USB DFU flash on AM62A.
In addition to the patches in this series, the following device-tree
changes will be required to test USB DFU on AM62A (bootph-all property
to be added to ensure that USB Controller is present at all stages
for DFU Boot):
https://gist.github.com/Siddharth-Vadapalli-at-TI/
53ba02cb0ff4a09c47e920d08247065f
The above device-tree changes will be made to the Linux device-tree,
which shall ensure that the same shall be a part of U-Boot device-tree
eventually.
The USB DFU config fragments for AM62x have been used for enabling
USB DFU boot on AM62a as follows:
R5 => am62ax_evm_r5_defconfig + am62x_r5_usbdfu.config
A53 => am62ax_evm_a53_defconfig + am62x_a53_usbdfu.config
Logs validating USB DFU boot with this series:
https://gist.github.com/Siddharth-Vadapalli-at-TI/
daa71da1b0e478a51afea42605fb2d2c
Link: https://lore.kernel.org/r/20241126120322.1760862-1-s-vadapalli@ti.com
Siddharth Vadapalli [Tue, 26 Nov 2024 12:03:19 +0000 (17:33 +0530)]
board: ti: am62ax: env: include environment for DFU
Include the TI K3 DFU environment to support DFU Boot and DFU Flash.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Siddharth Vadapalli [Tue, 26 Nov 2024 12:03:18 +0000 (17:33 +0530)]
usb: dwc3-generic: set "mode" based on caller of dwc3_generic_probe()
There are only two callers of "dwc3_generic_probe()", namely:
1. dwc3_generic_peripheral_probe()
2. dwc3_generic_host_probe()
Currently, the "mode" is set based on the device-tree node of the
platform device. Also, the DWC3 core doesn't support updating the "mode"
dynamically at runtime if it is set to "OTG", i.e. "OTG" is treated as a
separate mode in itself, rather than being treated as a mode which should
eventually lead to "host"/"peripheral".
Given that the callers of "dwc3_generic_probe()" clarify the expected
"mode" of the USB Controller, use that "mode" instead of the one
specified in the device-tree. This shall allow the USB Controller to
function both as a "Host" and as a "Peripheral" when the "mode" is "otg"
in the device-tree, based on the caller of "dwc3_generic_probe()".
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Tom Rini [Fri, 13 Dec 2024 20:12:46 +0000 (14:12 -0600)]
Merge patch series "J721S2: Enable ESMs and related PMIC"
Udit Kumar <u-kumar1@ti.com> says:
This enables the ESMs and the associated PMIC. Programming these bits is
a requirement to make the watchdog actually reset the board.
Logs
WDT reset J721S2
https://gist.github.com/uditkumarti/
93cfe863d1f3fe3abb82b1821105f274#file-j721s2-L2708
AM68 boot (this does not support WDT)
https://gist.github.com/uditkumarti/
93cfe863d1f3fe3abb82b1821105f274#file-am68
Link: https://lore.kernel.org/r/20241126053426.2627686-1-u-kumar1@ti.com
[trini: Merge configs/am68_sk_r5_defconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
Manorit Chawdhry [Tue, 26 Nov 2024 05:34:26 +0000 (11:04 +0530)]
configs: j721s2_evm_r5_defconfig: Add ESM configs
Enables ESM configs for j721s2 and disables them for AM68 as AM68
includes J721s2 configs by default.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Manorit Chawdhry [Tue, 26 Nov 2024 05:34:25 +0000 (11:04 +0530)]
arch: arm: dts: k3-j721s2-r5-common-proc-board: Add esm node
Add esm node for j721s2.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Keerthy [Tue, 26 Nov 2024 05:34:24 +0000 (11:04 +0530)]
board: ti: j721s2: Initialize the ESM & PMIC ESM
Initialize the 3 instances of SOC ESM & PMIC ESM.
This is needed for watchdog functionality.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Tom Rini [Fri, 13 Dec 2024 20:12:01 +0000 (14:12 -0600)]
Merge patch series "Add QOS support for J722S and AM62P"
Jayesh Choudhary <j-choudhary@ti.com> says:
Add QOS support for DSS in TI K3 SoC to route the DSS traffic through
RT queue by setting orderID as 15:
- J722S
- AM62P
Link: https://lore.kernel.org/r/20241126070614.47136-1-j-choudhary@ti.com
Jayesh Choudhary [Tue, 26 Nov 2024 07:06:14 +0000 (12:36 +0530)]
configs: am62p_evm_r5_defconfig: Enable CONFIG_K3_QOS
Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Jayesh Choudhary [Tue, 26 Nov 2024 07:06:13 +0000 (12:36 +0530)]
configs: j722s_evm_r5_defconfig: Enable CONFIG_K3_QOS
Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Jayesh Choudhary [Tue, 26 Nov 2024 07:06:12 +0000 (12:36 +0530)]
arm: mach-k3: am62p: Add QoS support for DSS
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
DDR intensive software applications can overwhelm the DSS's access to
the DDR because of their higher frequency DDR accesses. This can cause
flickering in display with certain applications running parallely if
the DSS traffic is being serviced through non-RT queue.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Jayesh Choudhary [Tue, 26 Nov 2024 07:06:11 +0000 (12:36 +0530)]
arm: mach-k3: j722s: Add QoS support for DSS
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
The C7x and VPAC can overwhelm the DSS's access to the DDR because of
their higher frequency DDR accesses. This can cause flickering in
display with certain edgeAI models running parallely if the DSS traffic
is being serviced through non-RT queue.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Tom Rini [Fri, 13 Dec 2024 03:07:26 +0000 (21:07 -0600)]
Revert "Merge patch series "vbe: Series part E""
This reverts commit
1fdf53ace13f745fe8ad4d2d4e79eed98088d555, reversing
changes made to
e5aef1bbf11412eebd4c242b46adff5301353c30.
I had missed that this caused too much size growth on rcar3_salvator-x.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 12 Dec 2024 22:35:47 +0000 (16:35 -0600)]
Merge patch series "vbe: Series part E"
Simon Glass <sjg@chromium.org> says:
This includes various patches towards implementing the VBE abrec
bootmeth in U-Boot. It mostly focuses on SPL tweaks and adjusting what
fatures are available in VPL.
Link: https://lore.kernel.org/r/20241207172412.1124558-1-sjg@chromium.org
Simon Glass [Sat, 7 Dec 2024 17:24:12 +0000 (10:24 -0700)]
hash: Plumb crc8 into the hash functions
Add an entry for crc8, with watchdog handling.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:11 +0000 (10:24 -0700)]
boot: Imply CRC8 with VBE
VBE uses a crc8 checksum to verify that the nvdata is valid, so make
sure it is available if VBE is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:10 +0000 (10:24 -0700)]
lib: Allow crc8 in TPL and VPL
Provide options to enable the CRC8 feature in TPL and VPL builds.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:09 +0000 (10:24 -0700)]
boot: Allow use of FIT in TPL and VPL
With VBE we want to use FIT in all phases of the boot. Add Kconfig
options to support this.
Disable the options for sandbox_vpl for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:08 +0000 (10:24 -0700)]
spl: lib: Allow for decompression in any SPL build
Add Kconfig symbols and update the Makefile rules so that decompression
can be used in TPL and VPL
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:07 +0000 (10:24 -0700)]
spl: Add some more debugging to load_simple_fit()
Add debugging of image-loading progress. Fix a stale comment in the
function comment while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:06 +0000 (10:24 -0700)]
spl: Drop a duplicate variable in boot_from_devices()
The variable 'ret' is defined twice, which is not intended. This may
have been a local merge error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes:
2eefeb6d893 ("spl: Report a loader failure")
Simon Glass [Sat, 7 Dec 2024 17:24:05 +0000 (10:24 -0700)]
spl: Drop use of uintptr_t
U-Boot uses ulong for addresses. It is confusing to use uintptr_t in a
few places, since it makes people wonder if the types are compatible.
Change the few occurences in SPL to use ulong
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:04 +0000 (10:24 -0700)]
spl: Support a relocated stack in any XPL phase
The current check looks only at SPL, but TPL or VPL might have a
different setting. Update the condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:03 +0000 (10:24 -0700)]
spl: Allow serial to be disabled in any XPL phase
The current check looks only at SPL, but TPL or VPL might have a
different setting. Update the condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:02 +0000 (10:24 -0700)]
spl: Report a loader failure
If a loader returns an error code it is silently ignored. Show a message
to at least provide some feedback to the user.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:01 +0000 (10:24 -0700)]
Support setting a maximum size for the VPL image
Add a size limit for VPL, to match those for SPL and TPL
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:24:00 +0000 (10:24 -0700)]
malloc: Provide a simple malloc for VPL
The VPL phase may want to use the smaller malloc() implementation, so
add an option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:23:59 +0000 (10:23 -0700)]
malloc: Show amount of used space when memory runs out
Show a bit more information when malloc() space is exhausted and
debugging is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:23:58 +0000 (10:23 -0700)]
boot: Respect the load_op in fit_image_load()
Some code has crept in which ignores this parameter. Fix this and add a
little debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes:
b1307f884a9 ("fit: Support compression for non-kernel components (e.g. FDT)")
Simon Glass [Sat, 7 Dec 2024 17:23:57 +0000 (10:23 -0700)]
bootstd: Avoid sprintf() in SPL when creating bootdevs
The name of the bootdev device is not that important, particular in SPL.
Save a little code space by using a simpler name.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:23:56 +0000 (10:23 -0700)]
boot: Allow FIT to fall back from best-match option
When the best-match feature fails to find something, use the provided
config name as a fallback. The allows SPL to select a suitable config
when best-match is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:23:55 +0000 (10:23 -0700)]
image: Add a prototype for fit_image_get_phase()
This function exists but is not exported. Add a prototype so it can be
used elsewhere.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 7 Dec 2024 17:23:54 +0000 (10:23 -0700)]
spl: mmc: Avoid size growth in spl_mmc_find_device() debug
The for() loop ends up being in the code even if the log_debug() does
nothing. Add a condition to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Sam Protsenko [Fri, 8 Mar 2024 00:04:32 +0000 (18:04 -0600)]
clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present
Sometimes clocks provided to a consumer might not have .set_rate
operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag
set. In that case it's usually possible to find a parent up the tree
which is capable of setting the rate (div, pll, etc). Implement a simple
lookup procedure for such cases, to traverse the clock tree until
.set_rate capable parent is found, and use that parent to actually
change the rate. The search will stop once the first .set_rate capable
clock is found, which is usually enough to handle most cases.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Tom Rini [Mon, 9 Dec 2024 22:29:47 +0000 (16:29 -0600)]
Merge tag 'v2025.01-rc4' into next
Prepare v2025.01-rc4
Tom Rini [Mon, 9 Dec 2024 22:09:28 +0000 (16:09 -0600)]
Prepare v2025.01-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 9 Dec 2024 14:46:57 +0000 (08:46 -0600)]
Merge tag 'u-boot-imx-next-
20241209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23736
- Add support for the NXP i.MX91 EVK board.
- Improve EEPRON suport on i.MX8MP DHCOM board.
- Switch phycore_imx8mm to using environment text files and improve
environment handling.
Tom Rini [Mon, 9 Dec 2024 14:46:33 +0000 (08:46 -0600)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
Marek Vasut [Thu, 28 Nov 2024 04:11:19 +0000 (05:11 +0100)]
arm64: renesas: Disable AVB1 and AVB2 on R8A779G0 V4H White Hawk board
The U-Boot is currently not capable of handling ethernet-phy-ieee802.3-c45
PHYs correctly, and also does not handle MDIO bus wide reset-gpios property.
Until proper C45 PHY support lands in U-Boot, disable AVB1/AVB2 interfaces.
This only disables the two MACs with 88Q2110/88Q2112 100/1000BASE-T1 PHYs
on ethenet sub-board, the main board AVB0 ethernet is unaffected.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Wed, 20 Nov 2024 09:48:30 +0000 (09:48 +0000)]
pinctrl: rzg2l: Drop unnecessary scope
In rzg2l_pinconf_set(), there are no new variables defined in the case
statement for PIN_CONFIG_INPUT_ENABLE so no additional scope is needed.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Wed, 20 Nov 2024 09:48:29 +0000 (09:48 +0000)]
pinctrl: rzg2l: Support Ethernet TXC output enable
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
signal is selectable to support an Ethernet PHY operating in either MII
or RGMII mode. By default, the signal is configured as an input and MII
mode is supported. The ETH_MODE register can be modified to configure
this signal as an output to support RGMII mode.
As this signal is be default an input, and can optionally be switched to
an output, it maps neatly onto an `output-enable` property in the device
tree.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Wed, 20 Nov 2024 09:48:28 +0000 (09:48 +0000)]
pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces
The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at
multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V.
rzg2l_pinconf_set() is extended to support the 2.5V setting, with a
check to ensure this is only used on Ethernet interfaces as it is not
supported on the SD & QSPI interfaces.
While we're modifying rzg2l_pinconf_set(), drop the unnecessary default
value for pwr_reg as it is set in every branch of the following if
condition.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Wed, 20 Nov 2024 09:49:39 +0000 (09:49 +0000)]
net: ravb: Simplify max-speed handling in ravb_of_to_plat
We can call dev_read_u32_default() instead of calling fdt_getprop() then
fdt32_to_cpu().
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Tue, 19 Nov 2024 19:36:26 +0000 (19:36 +0000)]
clk: rzg2l: Ignore enable for core clocks
In the RZ/G2L family, core clocks are always on and can't be disabled.
However, drivers which are shared with other SoCs may call clk_enable()
or clk_enable_bulk() for a clock referenced in the device tree which
happens to be a core clock on the RZ/G2L. To avoid the need for
conditionals in these drivers, simply ignore attempts to enable a core
clock.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Christoph Niedermaier [Fri, 6 Dec 2024 23:04:20 +0000 (00:04 +0100)]
board: dhelectronics: Sync env variable dh_som_serial_number with SN
The env variable "SN" is used to store the serial number on DH electronics
SoMs. New SoMs will use the variable "dh_som_serial_number". To ensure
compatibility, these env variables are synchronized. This is achieved
using callback functions.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Christoph Niedermaier [Fri, 6 Dec 2024 23:04:19 +0000 (00:04 +0100)]
lib: hashtable: Prevent recursive calling of callback functions
In case there are two variables which each implement env callback
that performs env_set() on the other variable, the callbacks will
call each other recursively until the stack runs out. Prevent such
a recursion from happening.
Example which triggers this behavior:
static int on_foo(...) { env_set("bar", 0); ... }
static int on_bar(...) { env_set("foo", 0); ... }
U_BOOT_ENV_CALLBACK(foo, on_foo);
U_BOOT_ENV_CALLBACK(bar, on_bar);
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Suggested-by: Marek Vasut <marex@denx.de>
Christoph Niedermaier [Fri, 6 Dec 2024 23:04:18 +0000 (00:04 +0100)]
arm64: imx8mp: Read values from M24C32-D write-lockable page on DHCOM i.MX8MP
The new i.MX8M Plus DHCOM rev.200 is populated with M24C32-D EEPROM
that contains an additional write-lockable page called ID page, which
is populated with a structure containing ethernet MAC addresses, DH
item number and DH serial number.
Because the write-lockable page is not present on rev.100 i.MX8MP DHCOM
SoM, test whether EEPROM ID page exists by setting up the i2c driver.
There may be multiple EEPROMs with an ID page on this platform, always
use the first one. The evaluation of the EEPROM ID page is done in two
steps. First, the content is read and checked. This is done to cache
the content of the EEPROM ID page. Second, the content is extracted
from the EEPROM buffer by requesting it.
For the ethernet MAC address the i.MX8M Plus DHCOM currently supports
parsing address from multiple sources in the following priority order:
1) U-Boot environment 'ethaddr'/'eth1addr' environment variable
2) SoC OTP fuses
3) On-SoM EEPROM
Add support for parsing the content of this new EEPROM ID page and place
it between 2) and 3) on the priority list. The new entry is 2.5) On-SoM
EEPROM write-lockable page.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Christoph Niedermaier [Fri, 6 Dec 2024 23:04:17 +0000 (00:04 +0100)]
arm64: dts: imx8mp: Add aliases for the access to the EEPROM ID page node
The new i.MX8M Plus DHCOM rev.200 is populated with M24C32-D EEPROM
that contains an additional write-lockable page called ID page. Add
aliases eeprom0wl and eeprom1wl for the access to the EEPROM ID
page node.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Peng Fan [Tue, 3 Dec 2024 15:42:54 +0000 (23:42 +0800)]
imx: Support i.MX91 11x11 EVK board
Add i.MX91 11x11 EVK Board support.
- Four ddr scripts included w/o inline ecc feature.
- SDHC/NETWORK/I2C/UART supported
- PCA9451 supported, default nominal drive mode
- Documentation added.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Tue, 3 Dec 2024 15:42:53 +0000 (23:42 +0800)]
arm64: dts: add NXP i.MX91 device tree
Add the i.MX91 device tree from [1]. These files could be synced
to linux upstream after [1] merged to linux source tree.
[1]
https://lore.kernel.org/all/
20241120094945.3032663-1-pengfei.li_1@nxp.com/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Tue, 3 Dec 2024 15:42:52 +0000 (23:42 +0800)]
pinctrl: imx93: support i.MX91
Reuse i.MX93 pinctrl driver for i.MX91, because i.MX91 follows same
design as i.MX93 in IOMUXC controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 3 Dec 2024 15:42:51 +0000 (23:42 +0800)]
ddr: imx: Add new rates for i.MX91
iMX91 reuses iMX93 controller and PHY, but with lower speed,
so add new DDR rates for i.MX91.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>