Aristo Chen [Tue, 22 Apr 2025 03:07:06 +0000 (11:07 +0800)]
doc: arch: arm64: fix typos
Fix typo from "recommened" to "recommended"
Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Aristo Chen [Sun, 20 Apr 2025 14:39:41 +0000 (22:39 +0800)]
doc: remove duplicated "commands"
The "commands" are duplicated, so remove one of them
Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Heinrich Schuchardt [Thu, 2 Jan 2025 18:11:33 +0000 (19:11 +0100)]
efi_loader: print image load address in StartImage
When starting image add the image load address to the debug output.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Heinrich Schuchardt [Thu, 2 Jan 2025 18:11:31 +0000 (19:11 +0100)]
efi_loader: build with HII configuration protocol
Without the HII configuration protocol the debug version of the UEFI shell
cannot be used.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Mattijs Korpershoek [Wed, 16 Apr 2025 12:36:28 +0000 (14:36 +0200)]
tools/make_pip: Use venv when invoking pip
Recent Ubuntu versions (24.04+) disallow pip by default when
installing packages. The recommended approach is to use a virtual
environment (venv) instead.
Because of this, "make pip" is failing on such versions.
To prepare CI container migration to Ubuntu 24.04, use a venv in the
make_pip script.
Note: This has been reported on [1]
[1] https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/37
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Tom Rini [Thu, 24 Apr 2025 22:02:48 +0000 (16:02 -0600)]
CI: Update to latest containers
This changes to using "venv" rather than "virtualenv" for Python
sandboxing.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 15 Apr 2025 18:10:26 +0000 (12:10 -0600)]
python: Use and refer to the venv module rather than virtualenv
Using some form of sandbox with Python modules is a long standing best
practice with the language. There are a number of ways to have a Python
sandbox be created. At this point in time, it seems the Python community
is moving towards using the "venv" module provided with Python rather
than a separate tool. To match that we make the following changes:
- Refer to a "Python sandbox" rather than virtualenv in comments, etc.
- Install the python3-venv module in our container and not virtualenv.
- In our CI files, invoke "python -m venv" rather than "virtualenv".
- In documentation, tell users to install python3-venv and not
virtualenv.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 24 Apr 2025 16:46:17 +0000 (10:46 -0600)]
Merge patch series "Add PCIe support for TI AM64 SoC"
Hrushikesh Salunke <h-salunke@ti.com> says:
TI's AM64 SoC has a single instance of Cadence PCIe Controller. This
series enables support for PCIe in AM64 SoC and to configure it in
Root-Complex mode of operation.
Link: https://lore.kernel.org/r/20250416120830.138965-1-h-salunke@ti.com
Hrushikesh Salunke [Wed, 16 Apr 2025 12:08:30 +0000 (17:38 +0530)]
configs: am64x_evm_a53_defconfig: Enable configs for PCIe support
TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which
is Cadence PCIe Controller. To support PCIe functionality with PCIe0
instance in Root-Complex mode enable corresponding configs. Also enable
configs to support NVMe over PCIe.
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Hrushikesh Salunke [Wed, 16 Apr 2025 12:08:29 +0000 (17:38 +0530)]
pci: pcie_cdns_ti: Enable PCIe root-complex mode in AM64 SoC
TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which
is Cadence PCIe Controller. Add support to configure PCIe0 in Root-
Complex mode of operation.
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Hrushikesh Salunke [Wed, 16 Apr 2025 12:08:28 +0000 (17:38 +0530)]
pci: pcie_cdns_ti: Include linux/sizes.h header
Driver uses macro SZ_4G to configure inbound base address register.
The macro is used without including the header file in which it is
defined. Fix this.
Fixes:
59ad5480098 ("pci: Add TI K3 Cadence PCIe Controller")
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Tom Rini [Thu, 24 Apr 2025 16:45:41 +0000 (10:45 -0600)]
Merge patch series "arm: mach-k3: remove some firewalls left over by ROM"
Bryan Brattlof <bb@ti.com> says:
This small series is here to remove some firewalls setup by ROM during
their boot and clean things up for Linux later on. Ideally this would be
a simple call to remove_fwl_configs() however the location of the
firewall is problematic (could potentially crash the core) when we're
currently executing from the memory region protected by the firewall.
So we need to introduce a function which allows us to disable specific
firewall regions and skip others to ensure boot stability.
Link: https://lore.kernel.org/r/20250414-firewalls-v1-0-89090085c08b@ti.com
Bryan Brattlof [Mon, 14 Apr 2025 20:20:03 +0000 (15:20 -0500)]
arm: mach-k3: am625: remove any firewalls ROM has configured for HSRAM
ROM will configure a firewall to only allow HSRAM to be touched by the
R5 core. Any outside entity like DMA or the A53s will not have access to
this region. This can be problematic when U-Boot, running on the A53,
loads firmware that runs out of this region.
To simplify things remove the firewall here and let the remote core
firmware place a new firewall themselves if they wish for the memory
region.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Bryan Brattlof [Mon, 14 Apr 2025 20:20:02 +0000 (15:20 -0500)]
arm: mach-k3: support disabling a single firewall region
During boot some firewall regions could contain the R5's code which if
we change the firewalls settings will crash the core. To get around this
issue, define a new function which allows us to specify specific regions
we want unlocked.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Tom Rini [Thu, 24 Apr 2025 16:44:59 +0000 (10:44 -0600)]
Merge patch series "More MMC fixes"
Judith Mendez <jm@ti.com> says:
This patch series fixes MMC_HS_52 mode in am654_sdhci driver,
as well as HIGH_SPEED_ENA and UHS_MODE_SELECT for HS modes.
Also add TI_COMMON_CMD_OPTIONS to K3 Sitara board a53 defconfigs.
Link: https://www.ti.com/lit/er/sprz574a/sprz574a.pdf
Link: https://lore.kernel.org/r/20250417234334.3661321-1-jm@ti.com
Judith Mendez [Thu, 17 Apr 2025 23:43:34 +0000 (18:43 -0500)]
configs: am62*_evm_a53_defconfig: Add TI_COMMON_CMD_OPTIONS
Add TI_COMMON_CMD_OPTIONS config options to Sitara K3 boards at
a53 stage since we rely on most of the commands implied for testing
and debugging purposes. Since all commands are now enabled by
default, remove the redundant CMD_* options in the a53 defconfigs.
Also add MMC_REG & MMC_SPEED_MODE_SET useful commands to
TI_COMMON_CMD_OPTIONS.
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Judith Mendez [Thu, 17 Apr 2025 23:43:33 +0000 (18:43 -0500)]
mmc: am654_sdhci: Add am654_sdhci_set_control_reg
This patch adds am654_sdhci_set_control_reg to am654_sdhci.
This is required to fix UHS_MODE_SELECT for TI K3 boards.
If any of HIGH_SPEED_ENA, V1P8_SIGNAL_ENA, UHS_MODE_SELECT
are set, then data will be launched on the pos-edge of the
clock.
Since K3 SoCs did not meet timing requirements for High Speed
SDR mode at rising clock edge, none of these three should be
set, therefore limit UHS_MODE_SELECT to only be set for modes
above MMC_HS_52.
This fixes MMC write issue on am64x evm at mode High Speed
SDR.
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Judith Mendez [Thu, 17 Apr 2025 23:43:32 +0000 (18:43 -0500)]
mmc: am654_sdhci: Fix HIGH_SPEED_ENA
High Speed enable bit switches data launch from the falling
clock edge (half cycle timing) to the rising clock edge (full
cycle timing). For all SD UHS modes, data launch must happen
at the rising clock edge, so set HIGH_SPEED_ENA for SDR12 and
SDR25 modes. For all HS modes, data launch must happen at the
falling clock edge, so do not set HIGH_SPEED_ENA for MMC_HS_52.
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Judith Mendez [Thu, 17 Apr 2025 23:43:31 +0000 (18:43 -0500)]
mmc: am654_sdhci: Add MMC_HS_52 to timing data
This patch adds MMC_HS_52 to the timing data structure.
Previously, this bus mode tap settings were not populated and
were instead populated for MMC_HS which is a different bus mode
up to 26MHz. Since we intended these settings according to the
device data sheet[0] for MMC_HS_52 up to 52MHz, populate MMC_HS
tap settings for MMC_HS_52.
While we are here, fix typo in ti,itap-del-sel-mms-hs.
[0] https://www.ti.com/lit/ds/symlink/am625.pdf Table 7-79
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Tom Rini [Thu, 24 Apr 2025 16:44:17 +0000 (10:44 -0600)]
Merge tag 'u-boot-dfu-
20250424' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-
20250425
Usb gadget:
- Fix ACM gadget release
- Allow ACM gadget restart after releasing it
- Add 'enabled' flag to usb_ep structure
DFU:
- Fix alt buffer clearing for DeveloperBox board
Sughosh Ganu [Wed, 19 Mar 2025 11:20:03 +0000 (16:50 +0530)]
cmd: cls: do not repeat clearing of console
There is no need to repeat the command to clear the console. Remove
it's repeat attribute.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Boon Khai Ng [Wed, 16 Apr 2025 03:17:51 +0000 (11:17 +0800)]
spi: cadence-qspi: Add disable STIG mode quikrs.
Adding quirk to disable STIG mode since cadence controller has
issue for read/write using the STIG mode. STIG mode is enabled
by default since 2023.04 for small read/write(<8bytes).
Updated STIG mode reading from dev_get_driver_data by assigning
to platdata struct before read quirks variable.
The STIG mode is disabled for normal read case and enabled
for QSPI Jedec ID read/write since it requires STIG read/write.
Porting from linux implementation
https://lore.kernel.org/all/
20241204063338.296959-1-niravkumar
.l.rabara@intel.com/T/
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Bhavya Kapoor [Tue, 15 Apr 2025 17:36:51 +0000 (23:06 +0530)]
arm: mach-k3: r5: j7200: Add clk dev data for WKUP UART
Add clk and dev data for wakeup uart to enable wakeup
UART as console.
Reported-by: KEERTHY <j-keerthy@ti.com>
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Daniel Schultz [Tue, 15 Apr 2025 15:12:41 +0000 (08:12 -0700)]
mach-k3: common_fdt: Move carveout struct
Labels are not allowed before declarations. Move the carveout struct
at the beginning and only update 'end' at this point.
This will fix following error:
arch/arm/mach-k3/common_fdt.c: In function 'fdt_fixup_reserved':
arch/arm/mach-k3/common_fdt.c:156:2: error: a label can only be part of a statement and a declaration is not a statement
156 | struct fdt_memory carveout = {
| ^~~~~~
make[1]: *** [scripts/Makefile.build:256: arch/arm/mach-k3/common_fdt.o] Error 1
make: *** [Makefile:1919: arch/arm/mach-k3] Error 2
Fixes:
096aa229a9e ("mach-k3: common_fdt: create a reserved memory node")
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Anshul Dalal [Tue, 15 Apr 2025 09:52:24 +0000 (15:22 +0530)]
mach-k3: add eMMC FS boot support for am62[ap]
This makes spl_mmc_boot_mode consistent across am62x, 62a and 62p.
If MMCSD_MODE_EMMCBOOT is returned, FS boot fails since it checks for FS
on the hardware partitions, not the UDA. So to allow FS boot from EMMC,
the function should return MMCSD_MODE_FS instead which allows us to read
from FS on the UDA.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Anshul Dalal [Tue, 15 Apr 2025 09:51:36 +0000 (15:21 +0530)]
arm: dts: am62a: allow booting from eMMC
The bootph-all property in u-boot enables driver initialization prior to
relocation, this is necessary to use the device as boot media.
sdhci0 is the phandle for eMMC on am62a, so this change allows us to use
eMMC as a boot media.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Anshul Dalal [Tue, 15 Apr 2025 09:50:27 +0000 (15:20 +0530)]
configs: set SPL_TEXT_BASE by default for k3 platforms
SPL_TEXT_BASE is used as the load address for the main domain SPL on k3
platforms.
Since the config value is the same for every board, this patch sets the
value 0x80080000 as default for all 64-bit ARCH_K3, 0x43c00000 as
default for the R5 cores and deletes the instances of SPL_TEXT_BASE in
individual defconfigs.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Love Kumar [Tue, 15 Apr 2025 09:41:09 +0000 (15:11 +0530)]
test/py: spi: Prevent to overwrite the reserved memory
Update SPI negative tests to prevent SF command from overwriting the
reserved memory area.
Signed-off-by: Love Kumar <love.kumar@amd.com>
Samuel Holland [Mon, 14 Apr 2025 19:47:04 +0000 (12:47 -0700)]
smbios: Do not look up children of invalid nodes
If there is no UCLASS_SYSINFO device available, parent_node will be
ofnode_null(). Calling ofnode_find_subnode() then triggers an assertion:
drivers/core/ofnode.c:598: ofnode_find_subnode: Assertion `ofnode_valid(node)' failed.
Check for a valid parent_node, not just that OF_CONTROL is enabled.
Fixes:
44ffb6f0ecaf ("smbios: Allow properties to come from the device tree")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Samuel Holland [Mon, 14 Apr 2025 19:30:11 +0000 (12:30 -0700)]
net: dwc_eth_qos: Fix hang when freeing packet after stop
If eqos_free_pkt() is called after eqos_stop(), eqos_stop_resets() will
have been called already. This may prevent accessing the MMIO space to
update the RX descriptor tail pointer, so we must skip the descriptor
maintenance logic. This is okay because the descriptors and tail pointer
will all be rewritten anyway during the next call to eqos_start().
This hang was observed after a failed TFTP transaction:
eqos_recv(dev=
000000047fb57330, flags=1):
eqos_recv: *packetp=
000000c3ffb5c080, length=151
TFTP error: 'file <FILE> not found for <IP>' (1)
Not retrying...
eqos_stop(dev=
000000047fb57330):
eqos_stop: OK
eqos_free_pkt(packet=
000000c3ffb5c080, length=151)
<HANG>
Fixes:
ba4dfef1469f ("net: add driver for Synopsys Ethernet QoS device")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Tom Rini [Wed, 23 Apr 2025 19:21:39 +0000 (13:21 -0600)]
Merge patch series "Uthreads"
Jerome Forissier <jerome.forissier@linaro.org> says:
This series introduces threads and uses them to improve the performance
of the USB bus scanning code and to implement background jobs in the
shell via two new commands: 'spawn' and 'wait'.
The threading framework is called 'uthread' and is inspired from the
barebox threads [2]. setjmp() and longjmp() are used to save and
restore contexts, as well as a non-standard extension called initjmp().
This new function is added in several patches, one for each
architecture that supports HAVE_SETJMP. A new symbol is defined:
HAVE_INITJMP. Two tests, one for initjmp() and one for the uthread
scheduling, are added to the lib suite.
After introducing threads and making schedule() and udelay() a thread
re-scheduling point, the USB stack initialization is modified to benefit
from concurrency when UTHREAD is enabled, where uthreads are used in
usb_init() to initialize and scan multiple busses at the same time.
The code was tested on arm64 and arm QEMU with 4 simulated XHCI buses
and some devices. On this platform the USB scan takes 2.2 s instead of
5.6 s. Tested on i.MX93 EVK with two USB hubs, one ethernet adapter and
one webcam on each, "usb start" takes 2.4 s instead of 4.6 s.
Finally, the spawn and wait commands are introduced, allowing the use of
threads from the shell. Tested on the i.MX93 EVK with a spinning HDD
connected to USB1 and the network connected to ENET1. The USB plus DHCP
init sequence "spawn usb start; spawn dhcp; wait" takes 4.5 seconds
instead of 8 seconds for "usb start; dhcp".
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=446674
[2] https://github.com/barebox/barebox/blob/master/common/bthread.c
Link: https://lore.kernel.org/r/20250418141114.2056981-1-jerome.forissier@linaro.org
Jerome Forissier [Fri, 18 Apr 2025 14:09:45 +0000 (16:09 +0200)]
configs: qemu: enable UTHREAD and CMD_SPAWN in various defconfigs
Enable UTHREAD and CMD_SPAWN on supported QEMU platforms for testing
purposes.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:44 +0000 (16:09 +0200)]
MAINTAINERS: add UTHREAD
Add myself as the maintainer for the UTHREAD framework, the spawn/wait
commands and the associated tests.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:43 +0000 (16:09 +0200)]
test: cmd: add test for spawn and wait commands
Test the spawn and wait commands.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:42 +0000 (16:09 +0200)]
cmd: add spawn and wait commands
Add a spawn command which runs another command in the background, as
well as a wait command to suspend the shell until one or more background
jobs have completed. The job_id environment variable is set by spawn and
wait accepts optional job ids, so that one can selectively wait on any
job.
Example:
=> date; spawn sleep 5; spawn sleep 3; date; echo "waiting..."; wait; date
Date: 2025-02-21 (Friday) Time: 17:04:52
Date: 2025-02-21 (Friday) Time: 17:04:52
waiting...
Date: 2025-02-21 (Friday) Time: 17:04:57
=>
Another example showing how background jobs can make initlizations
faster. The board is i.MX93 EVK, with one spinning HDD connected to
USB1 via a hub, and a network cable plugged into ENET1.
# From power up / reset
u-boot=> setenv autoload 0
u-boot=> setenv ud "usb start; dhcp"
u-boot=> time run ud
[...]
time: 8.058 seconds
# From power up / reset
u-boot=> setenv autoload 0
u-boot=> setenv ud "spawn usb start; spawn dhcp; wait"
u-boot=> time run ud
[...]
time: 4.475 seconds
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:41 +0000 (16:09 +0200)]
dm: usb: initialize and scan multiple buses simultaneously with uthread
Use the uthread framework to initialize and scan USB buses in parallel
for better performance. The console output is slightly modified with a
final per-bus report of the number of devices found, common to UTHREAD
and !UTHREAD. The USB tests are updated accordingly.
Tested on two platforms:
1. arm64 QEMU on a somewhat contrived example (4 USB buses, each with
one audio device, one keyboard, one mouse and one tablet)
$ make qemu_arm64_defconfig
$ make -j$(nproc) CROSS_COMPILE="ccache aarch64-linux-gnu-"
$ qemu-system-aarch64 -M virt -nographic -cpu max -bios u-boot.bin \
$(for i in {1..4}; do echo -device qemu-xhci,id=xhci$i \
-device\ usb-{audio,kbd,mouse,tablet},bus=xhci$i.0; \
done)
2. i.MX93 EVK (imx93_11x11_evk_defconfig) with two USB hubs, each with
one webcam and one ethernet adapter, resulting in the following device
tree:
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 100mA)
| GenesysLogic USB2.1 Hub
|
+-3 Vendor specific (480 Mb/s, 350mA)
| Realtek USB 10/100/1000 LAN
001000001
|
+-4 (480 Mb/s, 500mA)
HD Pro Webcam C920
8F7CD51F
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 100mA)
| USB 2.0 Hub
|
+-3 Vendor specific (480 Mb/s, 200mA)
| Realtek USB 10/100/1000 LAN 000001
|
+-4 (480 Mb/s, 500mA)
Generic OnLan-CS30
201801010008
Note that i.MX was tested on top of the downstream repository [1] since
USB doesn't work in the upstream master branch.
[1] https://github.com/nxp-imx/uboot-imx/tree/lf-6.6.52-2.2.0
commit
6c4545203d12 ("LF-13928 update key for capsule")
The time spent in usb_init() ("usb start" command) is reported on
the console. Here are the results:
| CONFIG_UTHREAD=n | CONFIG_UTHREAD=y
--------+------------------+-----------------
QEMU | 5628 ms | 2212 ms
i.MX93 | 4591 ms | 2441 ms
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:40 +0000 (16:09 +0200)]
dm: usb: move bus initialization into new static function usb_init_bus()
To prepare for the introduction of threads in the USB initialization
sequence, move code out of usb_init() into a new helper function:
usb_init_bus() and count the number of USB controllers initialized
successfully by using the DM device_active() function.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:39 +0000 (16:09 +0200)]
test: lib: add uthread_mutex test
Add a test for uthread mutexes.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:38 +0000 (16:09 +0200)]
test: lib: add uthread test
Add a thread framework test to the lib tests. Update the API
documentation to use the test as an example.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:37 +0000 (16:09 +0200)]
lib: time: hook uthread_schedule() into udelay()
Introduce a uthread scheduling loop into udelay() when CONFIG_UTHREAD
is enabled. This means that any uthread calling into udelay() may yield
to uthread and be scheduled again later. There is no delay in the
scheduling loop because tests have shown that such a delay can have a
detrimental effect on the console (input drops characters).
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:36 +0000 (16:09 +0200)]
cyclic: invoke uthread_schedule() from schedule()
Make the schedule() call from the CYCLIC framework a uthread scheduling
point too. This makes sense since schedule() is called from a lot of
places where uthread_schedule() needs to be called.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Jerome Forissier [Fri, 18 Apr 2025 14:09:35 +0000 (16:09 +0200)]
uthread: add uthread_mutex
Add struct uthread_mutex and uthread_mutex_lock(),
uthread_mutex_trylock(), uthread_mutex_unlock() to protect shared data
structures from concurrent modifications.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:34 +0000 (16:09 +0200)]
uthread: add cooperative multi-tasking interface
Add a new internal API called uthread (Kconfig symbol: UTHREAD) which
provides cooperative multi-tasking. The goal is to be able to improve
the performance of some parts of U-Boot by overlapping lengthy
operations, and also implement background jobs in the U-Boot shell.
Each uthread has its own stack allocated on the heap. The default stack
size is defined by the UTHREAD_STACK_SIZE symbol and is used when
uthread_create() receives zero for the stack_sz argument.
The implementation is based on context-switching via initjmp()/setjmp()/
longjmp() and is inspired from barebox threads [1]. A notion of thread
group helps with dependencies, such as when a thread needs to block
until a number of other threads have returned.
The name "uthread" comes from "user-space threads" because the
scheduling happens with no help from a higher privileged mode, contrary
to more complex models where kernel threads are defined. But the 'u'
may as well stand for 'U-Boot' since the bootloader may actually be
running at any privilege level and the notion of user vs. kernel may
not make much sense in this context.
[1] https://github.com/barebox/barebox/blob/master/common/bthread.c
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:33 +0000 (16:09 +0200)]
test: lib: add initjmp() test
Test the initjmp() function when HAVE_INITJMP is set. Use the test as an
example in the API documentation.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:32 +0000 (16:09 +0200)]
sandbox: add initjmp()
Add initjm[() to sandbox, a non-standard extension to setjmp()/
longjmp() allowing to initialize a jump buffer with a function pointer
and a stack pointer. This will be useful to later introduce threads.
With this new function it becomes possible to longjmp() to a particular
function pointer (rather than to a point previously reached during
program execution as is the case with setjmp()), and with a custom stack.
Both things are needed to spin off a new thread. Then the usual
setjmp()/longjmp() pair is enough to save and restore a context, i.e.,
switch thread. The implementation is taken verbatim from barebox [1] with
the exception of the additional stack_sz argument. It is quite complex
because contrary to U-Boot platform code we don't know how the system's
C library implements the jump buffer, so we can't just write the function
and stack pointers into it.
[1] https://github.com/barebox/barebox/blob/
b2a15c383ddc/arch/sandbox/os/setjmp.c
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:31 +0000 (16:09 +0200)]
riscv: add initjmp()
Implement initjmp() for RISC-V, a non-standard extension to setjmp()/
longjmp() allowing to initialize a jump buffer with a function pointer
and a stack pointer. This will be useful to later introduce threads.
With this new function it becomes possible to longjmp() to a particular
function pointer (rather than to a point previously reached during
program execution as is the case with setjmp()), and with a custom stack.
Both things are needed to spin off a new thread. Then the usual
setjmp()/longjmp() pair is enough to save and restore a context, i.e.,
switch thread.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:30 +0000 (16:09 +0200)]
arm: add initjmp()
Implement initjmp() for Arm. a non-standard extension to setjmp()/
longjmp() allowing to initialize a jump buffer with a function pointer
and a stack pointer. This will be useful to later introduce threads.
With this new function it becomes possible to longjmp() to a particular
function pointer (rather than to a point previously reached during
program execution as is the case with setjmp()), and with a custom stack.
Both things are needed to spin off a new thread. Then the usual
setjmp()/longjmp() pair is enough to save and restore a context, i.e.,
switch thread.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier [Fri, 18 Apr 2025 14:09:29 +0000 (16:09 +0200)]
arch: introduce initjmp() and Kconfig symbol HAVE_INITJMP
Add the HAVE_INIJMP symbol to be set by architectures that support
initjmp(), a non-standard extension to setjmp()/longjmp() allowing to
initialize a jump buffer with a function pointer and a stack pointer.
This will be useful to later introduce threads. With this new function
it becomes possible to longjmp() to a particular function pointer
(rather than to a point previously reached during program execution as
is the case with setjmp()), and with a custom stack. Both things are
needed to spin off a new thread. Then the usual setjmp()/longjmp() pair
is enough to save and restore a context, i.e., switch thread.
Add the initjmp() prototype to <include/setjmp.h> since it is common to
all architectures.
Add an entry to the API documentation: doc/api/setjmp.rst.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tom Rini [Wed, 23 Apr 2025 17:34:53 +0000 (11:34 -0600)]
Merge tag 'u-boot-rockchip-
20250423' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/25909
Please pull the updates for rockchip platform:
- New SoC support: RK3528, RK3576
- New Board support: rk3528 Radxa E20C, rk3576 Firefly ROC-RK3576-PC;
- Add generic board for rk3288 and rk3399;
- rng driver binding update;
- misc updates on board level or header files;
Tom Rini [Wed, 23 Apr 2025 14:57:13 +0000 (08:57 -0600)]
Merge tag 'mmc-2025-04-23' of https://source.denx.de/u-boot/custodians/u-boot-mmc
- Introducing back send_init_stream for omap_hsmmc
to perform the 74 clocks cycle sequence
- Move scmi regulator subnode hack to scmi_regulator
- Typo fix
Tom Rini [Wed, 23 Apr 2025 14:53:23 +0000 (08:53 -0600)]
Merge tag 'net-
20250423' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-
20250423
net:
- Make initr_net() invocation command line agnostic
net-legacy:
- net: dhcpv6: remove excluded middle expression
- net: dhcp6: Send DHCPv6 using multicast MAC
net-lwip:
- lwIP sandbox tests
misc:
- cmd: Remove CMD_NET protection
Jonas Karlman [Sun, 30 Mar 2025 17:20:35 +0000 (17:20 +0000)]
board: rockchip: Add minimal generic RK3399 board
Add a minimal generic RK3399 board that only have eMMC, SDMMC, SPI flash
and USB OTG enabled. This defconfig can be used to boot from eMMC,
SD-card or SPI flash on most RK3399 boards that follow reference board
design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 30 Mar 2025 17:20:34 +0000 (17:20 +0000)]
board: rockchip: Add minimal generic RK3328 board
Add a minimal generic RK3328 board that only have eMMC, SDMMC, SPI flash
and USB OTG enabled. This defconfig can be used to boot from eMMC,
SD-card or SPI flash on most RK3328 boards that follow reference board
design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:28 +0000 (23:51 +0200)]
rockchip: rk3576: Add support for ROC-RK3576-PC board
The ROC-RK3576-PC is a SBC made by Firefly, designed around the RK3576
SoC. This adds the needed board infrastructure and config for it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:27 +0000 (23:51 +0200)]
arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC
As the name implies, it is built around the RK3576 SoC with 4x Cortex-A72
cores, four Cortex-A53 cores and Mali-G52 MC3 GPU.
Storage options are EMMC, SD-Card, a 2242 M.2 slot and the possibility to
use UFS 2.0 storage.
Video Output options are a HDMI port, a DSI connector as well as Display-
Port via the TypeC connector (all of them not yet supported).
Networking options are a Low-profile Gigabit Ethernet RJ45 port with
Motorcomm YT8531 PHY as well as WiFi via an AMPAK AP6256 module.
USB ports on the board are 1x USB 3.0 port, 1x USB 2.0 port, 1x USB Type-C
and it comes with 40-pin GPIO header
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250210205126.1173631-3-heiko@sntech.de
[ upstream commit:
887ff17cdd8f088a52e2b61e71f2b6c9b9678de6 ]
(cherry picked from commit
388e7272d092bd20e414cd408bac39d8fd02d765)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:26 +0000 (23:51 +0200)]
dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC binding
Add devicetree binding for the ROC-RK3576-PC SBC.
The board is based on the RK3576 SoC (4*Cortex-A72 + 4*Cortex-A53).
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250210205126.1173631-2-heiko@sntech.de
[ upstream commit:
2be4a4171401761cb5fb02225d8b18351f6807c0 ]
(cherry picked from commit
89026942ddd0475d78b11b019285fff0c1d47266)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:25 +0000 (23:51 +0200)]
arm64: dts: rockchip: add rk3576 otp node
This adds the otp node to the rk3576 soc devicetree including the
individual fields we know about.
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250210224510.1194963-7-heiko@sntech.de
[ upstream commit:
8715d2eeb062f6859c252bb6c87b363230b66e9f ]
(cherry picked from commit
d67cf6de8aacb4abcdfb516eeb8a511a4a657bc1)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:24 +0000 (23:51 +0200)]
net: dwc_eth_qos_rockchip: Add support for RK3576
Add rk_gmac_ops and other special handling that is needed for GMAC to
work on RK3576.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:23 +0000 (23:51 +0200)]
mmc: rockchip_dw_mmc: Add support for rk3576
The rk3576 uses a different base-compatible, as starting with this
generation, the clock phase tuning is done via registers inside
the mmc controller and not from inside the CRU.
In U-Boot we do not tune at all, so no other code changes are
necessary.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:22 +0000 (23:51 +0200)]
mmc: rockchip_sdhci: Add support for RK3576
Add support for RK3576 to the rockchip sdhci driver.
It's pretty similar to its cousins found in the RK3568 and RK3588 and the
specific hs400-tx-tap number was taken from the vendor-u-boot.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:21 +0000 (23:51 +0200)]
rockchip: otp: Add support for RK3576
Add support for RK3576 compatible.
The RK3576 OTP uses the same read mechanism as the RK3588, just
with different values for offset and size.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:20 +0000 (23:51 +0200)]
ram: rockchip: Add rk3576 ddr driver support
Add ddr driver for rk3576 to get the ram capacity.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Elaine Zhang [Tue, 15 Apr 2025 21:51:19 +0000 (23:51 +0200)]
reset: rockchip: implement rk3576 lookup table
The current DT bindings for the rk3576 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.
This follows the implementation done in the Linux-Kernel and also
how the rk3588 does this both in the Linux-Kernel as well as U-Boot.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[adapted from mainline Linux code for u-boot]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Elaine Zhang [Tue, 15 Apr 2025 21:51:18 +0000 (23:51 +0200)]
clk: rockchip: Add rk3576 clk support
Add clock driver support for Rockchip RK3576 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[adapted to mainline u-boot]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Steven Liu [Tue, 15 Apr 2025 21:51:17 +0000 (23:51 +0200)]
pinctrl: rockchip: support rk3576 pinctrl
Add support for the rk3576 variant of pinctrl.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
[adapted to mainline u-boot]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Xuhui Lin [Tue, 15 Apr 2025 21:51:16 +0000 (23:51 +0200)]
arm: rockchip: Add RK3576 arch core support
The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72
and quad-core Cortex-A53 including 6TOPS NPU, Mali-G52 MC3, HDMI Out,
DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, UFS,
USB OTG 3.0, Type-C, USB 2.0, PCIe 2.1, SATA 3, Ethernet, SDIO3.0, I2C,
UART, SPI, GPIO and PWM.
Add arch core support for it.
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
[adapted for mainline u-boot]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Xuhui Lin [Tue, 15 Apr 2025 21:51:15 +0000 (23:51 +0200)]
rockchip: mkimage: Add rk3576 support
Add support for rk3576 package header in mkimage tool.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 15 Apr 2025 21:51:14 +0000 (23:51 +0200)]
rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions
Currently the sdram code for arm64 expects CFG_SYS_SDRAM_BASE to be 0.
The ram being in front and the device-area behind it.
The upcoming RK3576 uses a different layout, with the device area
in front the ram, which then also extends past the 4G mark.
Adapt both the generic zone definitions as well as the ATAG parser
to be usable on devices where CFG_SYS_SDRAM_BASE is not 0.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:47:03 +0000 (22:47 +0000)]
board: rockchip: Add Radxa E20C
The Radxa E20C is an ultra-compact network computer with a RK3528A SoC
that offers a wide range of networking capabilities.
Features tested on a Radxa E20C v1.104:
- SD-card boot
- eMMC boot
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:47:02 +0000 (22:47 +0000)]
board: rockchip: Add minimal generic RK3528 board
Add a minimal generic RK3528 board that only have eMMC and SD-card
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3528 boards that follow reference board design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:47:01 +0000 (22:47 +0000)]
net: dwc_eth_qos_rockchip: Add support for RK3528
Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.
Add initial support for the RK3528 GMAC variant.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:47:00 +0000 (22:47 +0000)]
phy: rockchip-inno-usb2: Add support for RK3528
Add support for the two USB2.0 PHYs use in the RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:59 +0000 (22:46 +0000)]
phy: rockchip-inno-usb2: Add support for clkout_ctl_phy
The 480m clk is controlled using regs in the PHY address space and not
in the USB GRF address space on e.g. RK3528 and RK3506.
Add a clkout_ctl_phy usb2phy_reg to handle enable/disable of the 480m
clk on these SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Lin Jinhan [Mon, 7 Apr 2025 22:46:58 +0000 (22:46 +0000)]
rng: rockchip: Add support for rkrng variant
Add support for rkrng variant, used by e.g. RK3528 and RK3576.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments for mainline.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:57 +0000 (22:46 +0000)]
adc: rockchip-saradc: Add support for RK3528
The Successive Approximation ADC (SARADC) in RK3528 uses the v2
controller and support:
- 10-bit resolution
- Up to 1MS/s sampling rate
- 4 single-ended input channels
- Current consumption: 0.5mA @ 1MS/s
Add support for the 4 channels of 10-bit resolution supported by SARADC
in RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:56 +0000 (22:46 +0000)]
rockchip: otp: Add support for RK3528
Add support for the OTP controller in RK3528. The OTPC is similar to the
OTPC in RK3568 and can use the same ops for reading OTP data.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:55 +0000 (22:46 +0000)]
mmc: rockchip_sdhci: Gate clock for glitch free phase switching
Enable clock stopping to gate clock during phase code change to ensure
glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
on RK3528.
POST_CHANGE_DLY
Time taken for phase switching and stable clock output.
- Less than 4-cycle latency
PRE_CHANGE_DLY
Maximum Latency specification between transmit clock and receive clock.
- Less than 4-cycle latency
TUNE_CLK_STOP_EN
Clock stopping control for Tuning and auto-tuning circuit. When enabled,
clock gate control output is pulled low before changing phase select
codes. This effectively stops the receive clock. Changing phase code
when clocks are stopped ensures glitch free phase switching.
- Clocks stopped during phase code change
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:54 +0000 (22:46 +0000)]
mmc: rockchip_sdhci: Add initial support for RK3528
Add initial support for SDHCI controller in RK3528.
Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this,
more work is needed to get the faster HS200/HS400/HS400ES modes working.
Variant tap and delay num is copied from vendor Linux tag
linux-6.1-stan-rkr5.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:53 +0000 (22:46 +0000)]
mmc: rockchip_sdhci: Extend variant configuration
RK3528 and RK3576 use different tap and delay num for cmdout and strbin.
Move tap and delay num for cmdout and strbin to driver data to prepare
for adding new SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:52 +0000 (22:46 +0000)]
arch: arm: rockchip: Add initial support for RK3528
Rockchip RK3528 is a ARM-based SoC with quad-core Cortex-A53.
Add initial arch support for the RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:51 +0000 (22:46 +0000)]
arm: dts: rockchip: Add rk3528-u-boot.dtsi
Add a rk3528-u-boot.dtsi extending the basic dts/upstream rk3528.dtsi
with bare minimum nodes to have a booting system from eMMC and SD-card.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Steven Liu [Mon, 7 Apr 2025 22:46:50 +0000 (22:46 +0000)]
pinctrl: rockchip: Add support for RK3528
Add pinctrl driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with adjustments
to use regmap_update_bits().
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Mon, 7 Apr 2025 22:46:49 +0000 (22:46 +0000)]
clk: rockchip: Add support for RK3528
Add clock driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments and fixes for mainline.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:48 +0000 (22:46 +0000)]
ram: rockchip: Add basic support for RK3528
Add support for reading DRAM size information from PMUGRF os_reg18 reg.
Compared to most Rockchip SoCs the RK3528 use os_reg18 for DRAM info,
instead of os_reg2.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yifeng Zhao [Mon, 7 Apr 2025 22:46:47 +0000 (22:46 +0000)]
rockchip: mkimage: Add support for RK3528
Add support for generating Rockchip Boot Image for RK3528.
Similar to RK3568, the RK3528 has 64 KiB SRAM and 4 KiB of it is
reserved for BootROM.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:46 +0000 (22:46 +0000)]
arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB).
Enable support for the onboard eMMC on Radxa E20C.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250305214108.1327208-4-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
3a01b5f14a8ae2d45aea5aeed30001ac1655de86 ]
(cherry picked from commit
bd4c8a1c08f92d863d89c0ddff59e5f5bc6a1e34)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:45 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add maskrom button to Radxa E20C
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the maskrom button using a adc-keys node, also add the
regulators used by SARADC controller.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-5-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
3a2819ee9c71d1c6388e456cc4eb042914d15d7e ]
(cherry picked from commit
460ef5b623e5fa69843305faf50f6b1a8e81e1cd)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:44 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add user button to Radxa E20C
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the user button using a gpio-keys node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
ad8afc8813567994164f2720189c819da8c22b99 ]
(cherry picked from commit
6793b56b79df26ab3323e5293b97577d0786ddb3)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:43 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add leds node to Radxa E20C
Radxa E20C has three gpio controlled leds (sys, wan and lan).
Add led nodes and set default trigger to heartbeat for the sys led and
netdev for the lan and wan leds.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-2-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
6a709e003492e9878d5f1357be0b2e1162e1e6a6 ]
(cherry picked from commit
a3556ede6b48c7760ac3608ad77601fca26d2ce0)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:42 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard
CH340B for debug console use.
Add pinctrl for UART0 M0 pins used for serial console.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
0d2312f0d3e4ce74af0977c1519a07dfc71a82ac ]
(cherry picked from commit
9bcf6ccdd87c3be48fe7d75150c6e403c5c0a42d)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:41 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add SDHCI controller for RK3528
The SDHCI controller in Rockchip RK3528 is similar to the one included
in RK3588.
Add device tree node for the SDHCI controller in RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250305214108.1327208-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
a98cc47f79ab5b8059b748bf0bd59335edfff7d9 ]
(cherry picked from commit
db7a99c423dea0ead19d6a18053d898a762a3b48)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:40 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add SARADC node for RK3528
Add a device tree node for the SARADC controller used by RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-4-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
6e58302c84ce90aadbecd41efe1f69098a6f91e5 ]
(cherry picked from commit
8ba64ba5cb301bca777ba7f0d2a2a72f49af5ff2)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chukun Pan [Mon, 7 Apr 2025 22:46:39 +0000 (22:46 +0000)]
arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
Add SCMI clk for CPU, GPU and RNG will also use it.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250307100008.789129-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
fbcbc1fb93e14729bd87ab386b7f62694dcc8b51 ]
(cherry picked from commit
6e03c7e28e2d929a420809a24b0379305a9fb86a)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chukun Pan [Mon, 7 Apr 2025 22:46:38 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add rk3528 QoS register node
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250306123809.273655-3-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
61a05d8ca3030a544175671f5fab7a8f29c24085 ]
(cherry picked from commit
9ee90dfd6957fcc42ea94c43d195b01d1b286713)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:37 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
a31fad19ae39ea27b5068e3b02bcbf30a905339b ]
(cherry picked from commit
89a24fa2e923b68a42ccc8cc9cb2d5bdf291ac40)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yao Zi [Mon, 7 Apr 2025 22:46:36 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add UART clocks for RK3528 SoC
Add missing clocks in UART nodes for RK3528 SoC.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
b9454434d0349223418f74fbfa7b902104da9bc5 ]
(cherry picked from commit
12f69f638472dc9cf1b62816c7d4407de1846d12)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yao Zi [Mon, 7 Apr 2025 22:46:35 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add clock generators for RK3528 SoC
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
858cdcdd11cf9913756297d3869e4de0f01329ea ]
(cherry picked from commit
60741472b42e92d2393327cb70669ab90e3b382f)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yao Zi [Mon, 7 Apr 2025 22:46:34 +0000 (22:46 +0000)]
dt-bindings: clock: Document clock and reset unit of RK3528
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
e0c0a97bc308f71b0934e3637ac545ce65195df0 ]
(cherry picked from commit
8768d063e732e64892e4d1d09aa583d1394c8388)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 8 Apr 2025 22:11:45 +0000 (22:11 +0000)]
rng: rockchip_rng: Update compatible for RK3588
Linux commit
6ee0b9ad3995 ("arm64: dts: rockchip: Add rng node to
RK3588") merged for v6.15-rc1 add a proper rng node to the device tree.
The compatible used differs compared to what U-Boot is currently using.
Replace the old trngv1 compatible with the dts/upstream compatible in
the rng driver and remove the old rng node compatible override from SoC
u-boot.dtsi to keep rng working after the driver change.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Nicolas Frattaroli [Tue, 8 Apr 2025 22:11:44 +0000 (22:11 +0000)]
arm64: dts: rockchip: Add rng node to RK3588
Add the RK3588's standalone hardware random number generator node to its
device tree, and enable it.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com
[changed reset-id to its numeric value while the constant makes its
way through the crypto tree]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit:
6ee0b9ad3995ee5fa229035c69013b7dd0d3634b ]
(cherry picked from commit
4800c4aaad00ffdc053850f130e8504a04dd110d)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>