From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat, 27 Oct 2012 13:50:28 +0000 (+0200)
Subject: drm/i915: clarify why we need to enable fdi plls so early
X-Git-Tag: v3.8-rc1~82^2~192^2~102
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fff367c752f5fb998882c7bc0a213ab1e53857db;p=pandora-kernel.git

drm/i915: clarify why we need to enable fdi plls so early

For reference, see "Graphics BSpec: vol4g North Display Engine
Registers [IVB], Display Mode Set Sequence", step 4 of the enabling
sequence:

a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency
b. "Switch from Rawclk to PCDclk in FDI Receiver
c. "Enable CPU FDI Transmitter PLL, wait for warmup"

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

Reading git-diff-tree failed