From: Shawn Guo Date: Mon, 4 Feb 2013 02:21:32 +0000 (+0800) Subject: regulator: anatop: improve precision of delay time X-Git-Tag: v3.9-rc1~154^2~21^2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ff1ce0571eb98b21f5a9221b2fdc3bd010840b1a;p=pandora-kernel.git regulator: anatop: improve precision of delay time For cpufreq example, it takes 13 steps (25 mV for one step) to increase vddcore from 0.95 V to 1.275 V, and the time of 64 clock cycles at 24 MHz for one step is ~2.67 uS, so the total delay time would be ~34.71 uS. But the current calculation in the driver gives 39 uS. Change the formula to have the addition of 1 be the last step, so that we can get a more precise delay time. For example above, the new formula will give 35 uS. Signed-off-by: Shawn Guo Signed-off-by: Mark Brown --- Reading git-diff-tree failed