From: Felipe Balbi <balbi@ti.com>
Date: Fri, 14 Oct 2011 10:00:30 +0000 (+0300)
Subject: usb: dwc3: workaround: U1/U2 -> U0 transiton
X-Git-Tag: v3.3-rc1~153^2~30^2~8
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fae2b904aa85beecd0950026de28921ae65fb3da;p=pandora-kernel.git

usb: dwc3: workaround: U1/U2 -> U0 transiton

RTL revisions <1.83a have an issue where, depending
on the link partner, the USB link might do multiple
entry/exit of low power states before a transfer
takes place causing degraded throughput.

The suggested workaround is to clear bits
12:9 of DCTL register if we see a transition
from U1|U2 to U0 and only re-enable that on
a transfer complete IRQ and we have no pending
transfers on any of the enabled endpoints.

Signed-off-by: Felipe Balbi <balbi@ti.com>
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