From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Fri, 27 Aug 2010 03:08:57 +0000 (+0800)
Subject: agp/intel: Fix cache control for Sandybridge
X-Git-Tag: v2.6.36-rc4~94^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337;p=pandora-kernel.git

agp/intel: Fix cache control for Sandybridge

Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.

And set cache control to always LLC only by default on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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