From: Sean Paul <seanpaul@chromium.org>
Date: Wed, 1 Oct 2014 16:40:41 +0000 (-0400)
Subject: clk: tegra124: Add init data for dsi lp clocks
X-Git-Tag: omap-for-v4.1/prcm-dts-mfd-syscon-fix~17^2~12^2~6
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f892f24b37345181b9bc7748ed4a8e927cdb6e06;p=pandora-kernel.git

clk: tegra124: Add init data for dsi lp clocks

Set the parent of the dsi lp clocks to pll_p and the rate
to 68MHz. The default parent is clk_m and rate is 12MHz, this
is too slow to receive data from the peripheral.

Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
will suffice.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---

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