From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Tue, 11 Feb 2014 17:52:06 +0000 (+0200)
Subject: drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB
X-Git-Tag: v3.14-rc4~28^2~4^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36;p=pandora-kernel.git

drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB

According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
in a single cacheline. Make sure that happens.

v2: Use intel_ring_begin_cacheline_safe()
v3: Use intel_ring_cacheline_align() (Chris)

Cc: Bjoern C <lkml@call-home.ch>
Cc: Alexandru DAMIAN <alexandru.damian@intel.com>
Cc: Enrico Tagliavini <enrico.tagliavini@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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