From: Paul Walmsley <paul@pwsan.com>
Date: Thu, 26 Jun 2008 07:09:13 +0000 (-0600)
Subject: OMAP3 clock: fix omap2_clk_wait_ready() for OMAP3430ES2+ DSS
X-Git-Tag: v2.6.26-omap1~95
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f4c458db2b615037f7c1fd91d238f6420e7b8f77;p=pandora-kernel.git

OMAP3 clock: fix omap2_clk_wait_ready() for OMAP3430ES2+ DSS

On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit.  This is a departure from previous silicon,
which only had an initiator standby bit.

This means we need to test the target idle bit after enabling
dss1_alwon_fclk.  Previous clock code has done the wrong thing since ES2
came out: it's either tested the wrong bit, causing

    Clock dss1_alwon_fck failed to enable in 100000 tries

messages, or not tested anything at all, causing crashes during DISPC
initialization with:

    Unhandled fault: external abort on non-linefetch (0x1028)

This patch modifies omap2_clk_wait_ready() to wait for the DSS to become
accessible after dss1_alwon_fclk, dss_l3_iclk, and dss_l4_iclk are enabled.

Thanks to Anand Gadiyar <gadiyar@ti.com> for identifying one of the
problem patches, Koen Kooi <k.kooi@student.utwente.nl> for testing a
previous version of this patch, and Dirk Behme
<dirk.behme@googlemail.com> for review of a previous version.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---

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