From: John Crispin <blogic@openwrt.org>
Date: Thu, 16 Aug 2012 08:25:42 +0000 (+0000)
Subject: MIPS: lantiq: enable pci clk conditional for xrx200 SoC
X-Git-Tag: v3.7-rc1~77^2~9^2~7
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f40e1f9d856ec417468c090c4b56826171daa670;p=pandora-kernel.git

MIPS: lantiq: enable pci clk conditional for xrx200 SoC

The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4235/
---

Reading git-diff-tree failed