From: Minghuan Lian Date: Fri, 21 Jun 2013 10:59:14 +0000 (+0800) Subject: powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3 X-Git-Tag: v3.12-rc1~123^2~110^2~9 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f31dd9443afd35696a833c2a32d584a9257abd40;p=pandora-kernel.git powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3 The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank contains 16 registers, and this patch adds NR_MSI_REG_MAX and NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank. MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1 uses different bits definition than MSIIR. This patch adds ibs_shift and srs_shift to indicate the bits definition of the MSIIR and MSIIR1, so the same code can handle the MSIIR and MSIIR1 simultaneously. Signed-off-by: Minghuan Lian [scottwood@freescale.com: reinstated static on all_avail] Signed-off-by: Scott Wood --- Reading git-diff-tree failed