From: Dylan Reid <dgreid@chromium.org>
Date: Mon, 3 Nov 2014 18:28:56 +0000 (-0800)
Subject: ASoC: max98090: Correct pclk divisor settings
X-Git-Tag: omap-for-v3.19/fixes-for-merge-window~85^2~2^2~1^7
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ece509c10985ba93ccc8c68f808a9e767250041c;p=pandora-kernel.git

ASoC: max98090: Correct pclk divisor settings

The Baytrail-based chromebooks have a 20MHz mclk, the code was setting
the divisor incorrectly in this case.  According to the 98090
datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20.
Correct this and the surrounding clock ranges as well to match the
datasheet.

Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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