From: Eric Yuen <eyuen@nvidia.com>
Date: Tue, 26 Aug 2014 15:11:37 +0000 (+0200)
Subject: PCI: tegra: Make sure the PCIe PLL is really reset
X-Git-Tag: omap-for-v3.19/prcm-cleanup~136^2~12^5~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ec73276204f06b6446a9c9b70173a1c15f6de536;p=pandora-kernel.git

PCI: tegra: Make sure the PCIe PLL is really reset

Depending on the prior state of the controller, the PLL reset may not be
pulsed.  Clear the register bit and set it after a small delay to ensure
that the PLL is really reset.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---

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