From: Ulf Hansson <ulf.hansson@linaro.org>
Date: Tue, 14 May 2013 13:14:55 +0000 (+0200)
Subject: mfd: db8500-prcmu: Update stored DSI PLL divider value
X-Git-Tag: v3.10-rc3~32^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e9d7b4b5691cac4dce6c5eed9e217e50e24edef7;p=pandora-kernel.git

mfd: db8500-prcmu: Update stored DSI PLL divider value

Previously the DSI PLL divider rate was initialised statically and
assumed to be 1. Before the common clock framework was enabled for
ux500, a call to clk_set_rate() would always update the HW registers
no matter what the current setting was.

This patch makes sure the actual hw settings and the sw assumed
settings are matched.

Signed-off-by: Paer-Olof Haakansson <par-olof.hakansson@stericsson.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
---

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