From: Nicolas Pitre <nicolas.pitre@linaro.org>
Date: Wed, 17 Jul 2013 00:59:53 +0000 (-0400)
Subject: ARM: vexpress/dcscb: fix cache disabling sequences
X-Git-Tag: v3.12-rc1~115^2~21^2~4
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e8f9bb1bd6bb93fff773345cc54c42585e0e3ece;p=pandora-kernel.git

ARM: vexpress/dcscb: fix cache disabling sequences

Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared.  Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
---

Reading git-diff-tree failed