From: Jesse Barnes Date: Fri, 15 Jun 2012 18:55:19 +0000 (-0700) Subject: agp/intel: allow cacheable and GDFT PTEs on ValleyView X-Git-Tag: v3.6-rc1~83^2~42^2~7 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e87c46993e30e8fe2e7a0981a532abe8bba07e62;p=pandora-kernel.git agp/intel: allow cacheable and GDFT PTEs on ValleyView The PTE format is similar to SNB, but we don't support an MLC and don't need chipset flushing. Note: I have my questions whether this is right, given that MLC died for snb & ivb, that ivb has grown a L3$ cache instead (which vlv seems to have, too) and that the LLC bit here isn't actually LLC, but just means 'snoop cpu caches'. But I plan to burn this all with the heat of a thousands suns in my gtt rework, so who cares ;-) Signed-off-by: Jesse Barnes [danvet: Added note.] Signed-off-by: Daniel Vetter --- Reading git-diff-tree failed