From: Huacai Chen Date: Thu, 26 Jun 2014 03:41:30 +0000 (+0800) Subject: MIPS: Add Loongson-3B support X-Git-Tag: cleanup-for-v3.18~94^2~67 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e7841be50fe2b8751a51a068b8cdcdcb6611e354;p=pandora-kernel.git MIPS: Add Loongson-3B support Loongson-3B is a 8-cores processor. In general it looks like there are two Loongson-3A integrated in one chip: 8 cores are separated into two groups (two NUMA node), each node has its own local memory. Of course there are some differences between one Loongson-3B and two Loongson-3A. E.g., the base addresses of IPI registers of each node are not the same; Loongson-3A use ChipConfig register to enable/disable clock, but Loongson-3B use FreqControl register instead. There are two revision of Loongson-3B, the first revision is called as Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the second revision is called as Loongson-3B1500, whose frequency is 1.5GHz and has a PRid 0x6307. Both revisions has a bug that clock cannot be disabled at runtime, but this will be fixed in future. Signed-off-by: Huacai Chen Cc: John Crispin Cc: Steven J. Hill Cc: Aurelien Jarno Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang Cc: Zhangjin Wu Patchwork: https://patchwork.linux-mips.org/patch/7188/ Signed-off-by: Ralf Baechle --- Reading git-diff-tree failed