From: Seungwon Jeon <tgih.jun@samsung.com>
Date: Tue, 22 May 2012 04:01:21 +0000 (+0900)
Subject: mmc: dw_mmc: correct the calculation for CLKDIV
X-Git-Tag: v3.5-rc4~28^2~6
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e419990b5e811027b1552cbc5b76a6cc180f7f48;p=pandora-kernel.git

mmc: dw_mmc: correct the calculation for CLKDIV

In case of "host->bus_hz < slot->clock", divider value is
miscalculated. And clock divider register value is multiple of 2. If
calculated divider value is odd number, result can be over-clocking.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Will Newton <will.newton@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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