From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Date: Wed, 10 Sep 2025 09:23:26 +0000 (+0900)
Subject: configs: qemu-sbsa: Define GIC register base address
X-Git-Tag: v2026.01-rc1~72^2~22^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e246e2b65885e6d5fd052ec2acdf2b07a53171f0;p=pandora-u-boot.git

configs: qemu-sbsa: Define GIC register base address

If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at
arch/arm/cpu/armv8/start.S.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---

diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h
index aff78160e12..669d0fe7c58 100644
--- a/include/configs/qemu-sbsa.h
+++ b/include/configs/qemu-sbsa.h
@@ -86,4 +86,8 @@
 #define CFG_SYS_INIT_RAM_ADDR		SBSA_MEM_BASE_ADDR
 #define CFG_SYS_INIT_RAM_SIZE		0x1000000
 
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			SBSA_GIC_DIST_BASE_ADDR
+#define GICR_BASE			SBSA_GIC_REDIST_BASE_ADDR
+
 #endif /* __CONFIG_H */