From: Jim Bride <jim.bride@linux.intel.com>
Date: Wed, 27 May 2015 17:21:48 +0000 (-0700)
Subject: drm/i915/hsw: Fix workaround for server AUX channel clock divisor
X-Git-Tag: omap-for-v4.3/legacy-v2-signed~255^2~1^2~4
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e058c945e03a629c99606452a6931f632dd28903;p=pandora-kernel.git

drm/i915/hsw: Fix workaround for server AUX channel clock divisor

According to the HSW b-spec we need to try clock divisors of 63
and 72, each 3 or more times, when attempting DP AUX channel
communication on a server chipset.  This actually wasn't happening
due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit
in status rather than checking that the operation was done and
that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.

[v2] Implemented alternate solution suggested by Jani Nikula.

Cc: stable@vger.kernel.org
Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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