From: Satheeshakrishna M Date: Fri, 22 Aug 2014 04:19:09 +0000 (+0530) Subject: drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence X-Git-Tag: omap-for-v4.2/fixes-rc1^2~17^2~58^2~38 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=dfb82408471ee2e56b26c05dcd50317f873bee57;p=pandora-kernel.git drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence Plug bxt PLL code into existing shared DPLL framework. v2: (imre) - squash in Satheeshakrishna's "Define BXT clock registers" and "Add state variables for bxt clock registers" patches - squash in Vandanas's "Change grp access to lane access for PLL" - fix group vs. lane access in bxt_ddi_pll_get_hw_state - add code comment why we read from lane registers while writing to group registers - clean up register macros - use BXT_PORT_PLL_* macros instead of open-coding the same - check if BXT_PORT_PCS_DW12_LN01 matches BXT_PORT_PCS_DW12_LN23 during hardware state readout - add missing LANESTAGGER_STRAP_OVRD masking - add note about missing step according to the latest BUN for PORT_PLL_9/lockthresh Signed-off-by: Satheeshakrishna M (v1) Signed-off-by: Imre Deak Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- Reading git-diff-tree failed