From: Kevin Cernekee <cernekee@gmail.com>
Date: Tue, 21 Oct 2014 04:28:00 +0000 (-0700)
Subject: MIPS: BMIPS: Add special cache handling in c-r4k.c
X-Git-Tag: omap-for-v3.19/fixes-rc1~122^2~107
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d74b0172e4e2cea34104ba6bdacb3cffe33eaf0f;p=pandora-kernel.git

MIPS: BMIPS: Add special cache handling in c-r4k.c

BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit,
so it isn't necessary to raise IPIs to keep both CPUs coherent.

BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$
fills from D$.  But a special sequence with 2 SYNCs and 32 NOPs is needed
to ensure coherency.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

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