From: John Linn <john.linn@xilinx.com>
Date: Wed, 2 Jul 2008 22:11:28 +0000 (-0700)
Subject: powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440
X-Git-Tag: v2.6.27-rc1~1058^2~14^2~4^2~7
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d58577d8f36f66dbb5dec30fc01dfddda0cfd1fa;p=pandora-kernel.git

powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440

The following changes add processing to initialize the Xilinx 16550 UART
in the boot wrapper for Virtex targets without firmware.  Normally the
boot wrapper assumes that the serial port has already been initialized by
firmware.

The wrapper was also modified to add the 440 build.

Signed-off-by: John Linn <john.linn@xilinx.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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