From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Fri, 4 Jul 2014 14:50:31 +0000 (-0300)
Subject: drm/i915: extract and improve gen8_irq_power_well_post_enable
X-Git-Tag: omap-for-v3.17/fixes-against-rc2~125^2~20^2~27
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d49bdb0e1054d022cc6f88fcecf9c79bae66eab0;p=pandora-kernel.git

drm/i915: extract and improve gen8_irq_power_well_post_enable

Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c
so we can reuse the nice IRQ macros we have there. The main difference
is that now we're going to check if the IIR register is non-zero when
we try to re-enable the interrupts.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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