From: Alexander Sverdlin Date: Thu, 11 Apr 2013 15:29:39 +0000 (+0200) Subject: MIPS: octeon: Fix GPIO number in IRQ chip private data X-Git-Tag: v3.10-rc1~15^2~2^2~30 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d41d547a419ca2d4df867a40a553abfe0c3df1d6;p=pandora-kernel.git MIPS: octeon: Fix GPIO number in IRQ chip private data Current GPIO chip implementation in octeon-irq is still broken, even after upstream commit 87161ccdc61862c8b49e75c21209d7f79dc758e9 (MIPS: Octeon: Fix broken interrupt controller code). It works for GPIO IRQs that have reset-default configuration, but not for edge-triggered ones. The problem is in octeon_irq_gpio_map_common(), which passes modified "hw" variable (which has range of possible values 16..31) as "gpio_line" parameter to octeon_irq_set_ciu_mapping(), which saves it in private data of the IRQ chip. Later, neither octeon_irq_gpio_setup() is able to re-configure GPIOs (cvmx_write_csr() is writing to non-existent CVMX_GPIO_BIT_CFGX), nor octeon_irq_ciu_gpio_ack() is able to acknowledge such IRQ, because "mask" is incorrect. Fix is trivial and has been tested on Cavium Octeon II -based board, including both level-triggered and edge-triggered GPIO IRQs. Signed-off-by: Alexander Sverdlin Cc: David Daney Acked-by: David Daney Patchwork: http://patchwork.linux-mips.org/patch/4980/ Acked-by: John Crispin --- Reading git-diff-tree failed