From: Satheeshakrishna M Date: Thu, 13 Nov 2014 14:55:18 +0000 (+0000) Subject: drm/i915/skl: Define shared DPLLs for Skylake X-Git-Tag: omap-for-v3.19/fixes-rc1~80^2~14^2~76 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d1a2dc7835f1258ac91cbdd8da1bc97b029b80f7;p=pandora-kernel.git drm/i915/skl: Define shared DPLLs for Skylake On skylake, DPLL 1, 2 and 3 can be used for DP and HDMI. The shared dpll framework allows us to share those DPLLs among DDIs when possible. The most tricky part is to provide a DPLL state that can be easily compared. DPLL_CRTL1 is shared by all the DPLLs, 6 bits each. The per-dpll crtl1 field of the hw state is then normalized to be the same value if 2 DPLLs do indeed have identical values for those 6 bits. v2: Port the code to the shared DPLL infrastructure (Damien) v3: Rebase on top of Ander's clock computation staging work for atomic (Damien) Reviewed-by: Paulo Zanoni (v2) Signed-off-by: Satheeshakrishna M (v1) Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- Reading git-diff-tree failed