From: Jane Wan Date: Wed, 16 Apr 2014 20:09:39 +0000 (-0700) Subject: spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT X-Git-Tag: omap-for-v3.16/fixes-against-rc1~39^2~29^2~2^4~1 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d0fb47a5237d8b9576113568bacfd27892308b62;p=pandora-kernel.git spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT Make FSL eSPI CSnBEF and CSnAFT fields in ESPI_SPMODEn registers (n=0,1,2,3) configurable through device tree. CSnBEF is the chip select setup time. It's the delay in bits from the activation of chip select pin to the first clock for data frame. CSnAFT is the chip select hold time. It's the delay in bits from the last clock for data frame to the deactivation of chip select pin. The FSL eSPI driver hardcodes CSnBEF and CSnAFT to 0. Need to set them to a different value for some device. Signed-off-by: Jane Wan Signed-off-by: Mark Brown --- Reading git-diff-tree failed