From: Robert Richter Date: Tue, 23 Mar 2010 18:33:21 +0000 (+0100) Subject: oprofile/x86: reserve counter msrs pairwise X-Git-Tag: v2.6.35-rc1~523^2~6 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d0e4120fda6f87eead438eed4d49032e12060e58;p=pandora-kernel.git oprofile/x86: reserve counter msrs pairwise For AMD's and Intel's P6 generic performance counters have pairwise counter and control msrs. This patch changes the counter reservation in a way that both msrs must be registered. It joins some counter loops and also removes the unnecessary NUM_CONTROLS macro in the AMD implementation. Signed-off-by: Robert Richter --- Reading git-diff-tree failed