From: Paul Walmsley <paul@pwsan.com>
Date: Sat, 20 Jun 2009 01:08:27 +0000 (-0600)
Subject: OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
X-Git-Tag: v2.6.31-rc1~54^2~4^2~5
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d0ba3922ae241a87d22a1c3ffad72b96fe993c9a;p=pandora-kernel.git

OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change

Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency.  Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
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