From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Fri, 26 Oct 2012 08:58:12 +0000 (+0200)
Subject: drm/i915: Write the FDI RX TU size reg at the right time
X-Git-Tag: v3.8-rc1~82^2~192^2~103
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cd986abbac6044c76b95fd512bc62329ef9959d0;p=pandora-kernel.git

drm/i915: Write the FDI RX TU size reg at the right time

According to "Graphics BSpec: vol4g North Display Engine Registers [IVB],
Display Mode Set Sequence" We need to write the TU size register
of the fdi RX unit _before_ starting to train the link.

Note: The current code is actually correct as Paulo mentioned in
review, but it's a bit confusion since only the fdi rx/tx plls need to
be enabled before the cpu pipes/planes. Hence it's still a good idea
to move the TU_SIZE setting to the "right" spot in the sequence, to
better match Bspec.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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