From: Nick Kossifidis <mickflemm@gmail.com>
Date: Sat, 7 Dec 2013 02:17:40 +0000 (+0000)
Subject: ath5k: Reset Tx interrupt bits also on PISR
X-Git-Tag: v3.14-rc1~94^2~482^2^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cb161cda634ae5fdb4de797096ba9028171507d2;p=pandora-kernel.git

ath5k: Reset Tx interrupt bits also on PISR

Some cards don't update the PISR properly when all SISR bits
for Tx interrupts are being cleared and as a result we get
interrupt storm. Since we handle all tx queues all together
(so we don't really use the SISR bits to do per-queue interrupt
handling), we can manualy update PISR by doing a write-to-clear
on its Tx interrupt bits.

Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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