From: Nate Case <ncase@xes-inc.com>
Date: Wed, 10 Jun 2009 20:37:28 +0000 (-0500)
Subject: powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs
X-Git-Tag: v2.6.31-rc1~110^2~29
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cab888e678d0986ebce95464d3842a6aeca1e3d8;p=pandora-kernel.git

powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs

Some boot loaders may not enable L1 instruction/data cache.  Check if
data and instruction caches are enabled, and enable them if needed.

Signed-off-by: Nate Case <ncase@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

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