From: Akash Goel <akash.goel@intel.com>
Date: Mon, 24 Mar 2014 17:30:07 +0000 (+0530)
Subject: drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
X-Git-Tag: omap-for-v3.16/fixes-against-rc1~44^2~10^2~24
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c98f50628722e2e287656bc7e7492e3d3a0726b8;p=pandora-kernel.git

drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv

For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.

v2: Modifying the comments and the patch commit message (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Apply checkpatch fixup.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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