From: Paul Walmsley <paul@pwsan.com>
Date: Sat, 20 Jun 2009 01:08:26 +0000 (-0600)
Subject: OMAP3 clock: add a short delay when lowering CORE clk rate
X-Git-Tag: v2.6.31-rc1~54^2~4^2~6
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c9812d042a21eb492a36cfabf9f41107f5ecee3d;p=pandora-kernel.git

OMAP3 clock: add a short delay when lowering CORE clk rate

When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
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