From: Brad Volkin <bradley.d.volkin@intel.com>
Date: Tue, 17 Jun 2014 21:10:34 +0000 (-0700)
Subject: drm/i915: Add some L3 registers to the parser whitelist
X-Git-Tag: omap-for-v3.17/fixes-against-rc2~125^2~63^2~20
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c9224faa59c3071ecfa2d4b24592f4eb61e57069;p=pandora-kernel.git

drm/i915: Add some L3 registers to the parser whitelist

Beignet needs these in order to program the L3 cache config for
OpenCL workloads, particularly when using SLM.

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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