From: Roy Spliet <r.spliet@student.tudelft.nl>
Date: Mon, 9 Jan 2012 05:23:07 +0000 (+1000)
Subject: drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation
X-Git-Tag: v3.4-rc1~143^2~61^2~40
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c7c039fd31be82ecb8d48477955e76badd38141a;p=pandora-kernel.git

drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation

Roy Spliet:
- Implement according to specs
- Simplify
- Make array for mc latency registers

Martin Peres:
- squash and split all the commits from Roy
- rework following Ben Skeggs comments
- add a form of timings validation
- store the initial timings for later use

Ben Skeggs
- merge slightly modified tidy-up patch with this one
- remove perflvl-dropping logic for the moment

Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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