From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed, 15 Dec 2010 09:56:50 +0000 (+0000)
Subject: Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"
X-Git-Tag: v2.6.38-rc1~419^2~23^2~11
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c6df541c00e53a4fdff7a130d4365f848075adcc;p=pandora-kernel.git

Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"

Restore PIPE_CONTROL once again just for Ironlake, as it appears that
MI_USER_INTERRUPT does not have the same coherency guarantees, that is
on Ironlake the interrupt following a GPU write is not guaranteed to
arrive after the write is coherent from the CPU, as it does on the
other generations.

Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reported-by: Shuang He <shuang.he@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32402
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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