From: Paul Mackerras Date: Fri, 10 Aug 2007 04:07:38 +0000 (+1000) Subject: [POWERPC] Handle alignment faults on new FP load/store instructions X-Git-Tag: v2.6.24-rc1~1450^2~351 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c6d4267eced79775399f256fbb4adb671e9b597e;p=pandora-kernel.git [POWERPC] Handle alignment faults on new FP load/store instructions This adds code to handle alignment traps generated by the following new floating-point load/store instructions, by emulating the instruction in the kernel (as is done for other instructions that generate alignment traps): lfiwax load floating-point as integer word algebraic indexed stfiwx store floating-point as integer word indexed lfdp load floating-point double pair lfdpx load floating-point double pair indexed stfdp store floating-point double pair stfdpx store floating-point double pair indexed All these except stfiwx are new in POWER6. lfdp/lfdpx/stfdp/stfdpx load and store 16 bytes of memory into an even/odd FP register pair. In little-endian mode each 8-byte value is byte-reversed separately (i.e. not as a 16-byte unit). lfiwax/stfiwx load or store the lower 4 bytes of a floating-point register from/to memory; lfiwax sets the upper 4 bytes of the FP register to the sign extension of the value loaded. Signed-off-by: Paul Mackerras --- Reading git-diff-tree failed