From: Peter 'p2' De Schrijver Date: Mon, 20 Dec 2010 20:05:07 +0000 (-0600) Subject: OMAP3630: PM: Disable L2 cache while invalidating L2 cache X-Git-Tag: v2.6.38-rc1~469^2~16^2~9^2~9 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c4236d2e7913d18d058a018f0d19473eb6a11a3c;p=pandora-kernel.git OMAP3630: PM: Disable L2 cache while invalidating L2 cache While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side". Cc: Kevin Hilman Cc: Tony Lindgren Acked-by: Jean Pihet Acked-by: Santosh Shilimkar [nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630] Signed-off-by: Nishanth Menon Signed-off-by: Eduardo Valentin Signed-off-by: Peter 'p2' De Schrijver Signed-off-by: Kevin Hilman --- Reading git-diff-tree failed