From: Eric Miao <eric.miao@marvell.com>
Date: Mon, 8 Dec 2008 10:35:03 +0000 (+0800)
Subject: [ARM] pxafb: allow better platform configurable smart panel timing
X-Git-Tag: v2.6.29-rc1~559^2~3^2~10
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c1f99c215c58111629984a49ba87b2b145dd1f5b;p=pandora-kernel.git

[ARM] pxafb: allow better platform configurable smart panel timing

For smart panels (LCD panel with internal framebuffer), the following
LCCR3 register bits have different meanings than the parallel one:

  LCCR3_PCP - controls the L_PCLK_WR polarity
  LCCR3_HSP - controls the L_LCLK_A0 polarity
  LCCR3_VSP - controls the L_FCLK_RD polarity

To keep minimum change to the original parallel timing, the .lcd_conn
flags and 'pxafb_mode_info.sync' are re-used to reflect this:

  LCD_PCLK_EDGE_{RISE,FALL} - configures LCCR3_PCP
  sync & FB_SYNC_{HOR,VERT}_HIGH_ACT - configures LCCR3_{HSP,VSP}

Signed-off-by: Eric Miao <eric.miao@marvell.com>
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