From: Sekhar Nori <nsekhar@ti.com>
Date: Wed, 20 Jun 2012 17:40:13 +0000 (+0530)
Subject: ARM: davinci: da8xx: fix interrupt handling
X-Git-Tag: v3.6-rc1~148^2~2^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=bbb33445b9cdd5ac7609723fcfc28dfa77a11039;p=pandora-kernel.git

ARM: davinci: da8xx: fix interrupt handling

CP_INTC code in entry-macro.S code reads SECR1n register to see if
an interrupt was indeed pending. This register is actually marked as
write-only in the OMAP-L138 TRM. Moreover, the code just checks to see
the entire register is non-zero and does not check a specific interrupt
number.

Fix this to use interrupt pending bit in GIPR register for this purpose.
GIPR register is already being read to know the highest priority interrupt
pending.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---

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