From: Boris Ostrovsky Date: Thu, 14 Mar 2013 21:10:41 +0000 (-0400) Subject: x86, MCE, AMD: Use MCG_CAP MSR to find out number of banks on AMD X-Git-Tag: omap-for-v3.10/dt-fixes-for-merge-window~107^2~2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=bafcdd3b6cb86035cdb0511450961edcdc084c27;p=pandora-kernel.git x86, MCE, AMD: Use MCG_CAP MSR to find out number of banks on AMD Currently number of error reporting register banks is hardcoded to 6 on AMD processors. This may break in virtualized scenarios when a hypervisor prefers to report fewer banks than what the physical HW provides. Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0] that's what we should use. Signed-off-by: Boris Ostrovsky Link: http://lkml.kernel.org/r/1363295441-1859-3-git-send-email-boris.ostrovsky@oracle.com [ reverse NULL ptr test logic ] Signed-off-by: Borislav Petkov --- Reading git-diff-tree failed