From: Samuel Holland Date: Tue, 31 Oct 2023 05:37:20 +0000 (-0500) Subject: riscv: Weakly define invalidate_icache_range() X-Git-Tag: v2024.01-rc2~11^2~9 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=bade208b5deb16120c6236e941c6e5f081e86c05;p=pandora-u-boot.git riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland Reviewed-by: Leo Yu-Chi Liang --- diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index c46b49eb0ac..afad7e117f3 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end) { } -void invalidate_icache_range(unsigned long start, unsigned long end) +__weak void invalidate_icache_range(unsigned long start, unsigned long end) { /* * RISC-V does not have an instruction for invalidating parts of the