From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 08:39:20 +0000 (+0800)
Subject: arm: dts: mt7629: fix sgmii clock selection for ethernet
X-Git-Tag: v2025.04-rc1~17^2~12^2~8
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ba365c3d23411620d86b5baf621c8f5a4000ab33;p=pandora-u-boot.git

arm: dts: mt7629: fix sgmii clock selection for ethernet

Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow
sgmiisys1 work correctly.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---

diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index 7dea7809c70..cd8277deafe 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -314,8 +314,10 @@
 				"sgmii2_cdr_ref", "sgmii2_cdr_fb",
 				"sgmii_ck", "eth2pll";
 		assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
-				  <&topckgen CLK_TOP_F10M_REF_SEL>;
+				  <&topckgen CLK_TOP_F10M_REF_SEL>,
+				  <&topckgen CLK_TOP_SGMII_REF_1_SEL>;
 		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
+					 <&topckgen CLK_TOP_SYSPLL4_D16>,
 					 <&topckgen CLK_TOP_SGMIIPLL_D2>;
 		power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
 		resets = <&ethsys ETHSYS_FE_RST>;