From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Thu, 26 Sep 2013 01:18:13 +0000 (-0400)
Subject: clk: keystone: add Keystone PLL clock driver
X-Git-Tag: omap-for-v3.13/fixes-for-merge-window-take2~11^2~5
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9;p=pandora-kernel.git

clk: keystone: add Keystone PLL clock driver

Add the driver for the PLL IPs found on Keystone 2 devices. The PLL
IP typically has a multiplier, a divider and a post-divider. The PLL IPs like
ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where
as the Main PLL is controlled by a PLL controller and memory map registers.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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