From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Tue, 23 Oct 2012 20:30:05 +0000 (-0200)
Subject: drm/i915: set the correct eDP aux channel clock divider on DDI
X-Git-Tag: v3.8-rc1~82^2~192^2~116
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b8fc2f6a18052194c486b407765a4f5e4dca692d;p=pandora-kernel.git

drm/i915: set the correct eDP aux channel clock divider on DDI

The cdclk frequency is not always the same, so the value here should
be adjusted to match it.

Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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