From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Tue, 6 Nov 2012 00:58:07 +0000 (+0100)
Subject: ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl
X-Git-Tag: omap-for-v3.8/fixes-for-merge-window-v4-signed~53^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b8db6b886a1fecd6a5b1d13b190f3149247305ef;p=pandora-kernel.git

ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com>

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---

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