From: Mark Langsdorf <mark.langsdorf@calxeda.com>
Date: Mon, 28 Jan 2013 16:13:13 +0000 (+0000)
Subject: clk / highbank: Prevent glitches in non-bypass reset mode
X-Git-Tag: v3.9-rc1~146^2~3^2~37
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b5964708532f4713e9cfb1b8b1a6ac8544fc66af;p=pandora-kernel.git

clk / highbank: Prevent glitches in non-bypass reset mode

The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---

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