From: Dirk Behme Date: Fri, 26 Apr 2013 08:13:56 +0000 (+0200) Subject: ARM: i.MX6: add i.MX6 specific L2 cache configuration X-Git-Tag: omap-for-v3.11/fixes-for-merge-window~69^2~10^2~27 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b3a9c315378ff811bf34393f2f0a6e8b9ffced3b;p=pandora-kernel.git ARM: i.MX6: add i.MX6 specific L2 cache configuration To improve the performance and power consumption add an i.MX6 specific L2 cache initialization. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] with two additional improvements: a) The L2X0_POWER_CTRL has only the two bits we set. So no need to read the register before. Remove the register read done in Freescale's patch. b) In the L2X0_PREFETCH_CTRL register, besides the double linefill (bit[30]), additionally enable the instruction and data prefetch (bit[29-28]). Signed-off-by: Dirk Behme Signed-off-by: Shawn Guo [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1 --- Reading git-diff-tree failed