From: weijun yang <york.yang@csr.com>
Date: Sun, 15 Feb 2015 15:43:51 +0000 (+0800)
Subject: mmc: sirf: update sdhci_sirf_execute_tuning procedure
X-Git-Tag: omap-for-v4.2/o2_dc~168^2~70
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b36ac1b43ebcd8b63cbfb35c54edb7bd577ad15b;p=pandora-kernel.git

mmc: sirf: update sdhci_sirf_execute_tuning procedure

For the original tuning code, delay value is set to SD Bus Clock Delay
Register (SD_CLK_DELAY_SETTING) as (val | (Val << 7) | (val << 16)),
which means CLK_DELAY_IN1, CLK_DELAY_IN2 and CLK_DELAY_OUT are the
same and with 128 steps. This is doubtful. In CSR design specification
documents CS-304575-DR-3H, this issue is clarified, the delay[13:0] in
SD_CLK_DELAY_SETTING is simplied to the concatenation of {CLK_DELAY_IN2,
CLK_DELAY_IN1}.
Besides, for CMD19 tuning, no need to set CLK_DELAY_OUT([22,16]
of SD_CLK_DELAY_SETTING).

Signed-off-by: weijun yang <york.yang@csr.com>
Signed-off-by: Barry Song <baohua.song@csr.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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